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Contents

README

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SN74HCT573PWR

Texas Instruments · Latches · TSSOP-20

SN74HCT573PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output-enable. When high, all eight Q outputs are in high-impedance (Hi-Z) state; when low, outputs are driven. Does not affect internal latch operation.
2 1D input Data input for latch 1 (TTL-compatible). Latched into 1Q on falling edge of LE.
3 2D input Data input for latch 2 (TTL-compatible). Latched into 2Q on falling edge of LE.
4 3D input Data input for latch 3 (TTL-compatible). Latched into 3Q on falling edge of LE.
5 4D input Data input for latch 4 (TTL-compatible). Latched into 4Q on falling edge of LE.
6 5D input Data input for latch 5 (TTL-compatible). Latched into 5Q on falling edge of LE.
7 6D input Data input for latch 6 (TTL-compatible). Latched into 6Q on falling edge of LE.
8 7D input Data input for latch 7 (TTL-compatible). Latched into 7Q on falling edge of LE.
9 8D input Data input for latch 8 (TTL-compatible). Latched into 8Q on falling edge of LE.
10 GND power_in Ground reference (0 V). Connect to system ground.
11 LE input Latch-enable. When high, Q outputs follow D inputs (transparent); when low, outputs are latched at the last D value. Setup 10 ns / hold 5 ns at Vcc=4.5 V.
12 8Q tri_state 3-state latched output 8. Drives ±6 mA at 5 V; Hi-Z when OE is high.
13 7Q tri_state 3-state latched output 7. Drives ±6 mA at 5 V; Hi-Z when OE is high.
14 6Q tri_state 3-state latched output 6. Drives ±6 mA at 5 V; Hi-Z when OE is high.
15 5Q tri_state 3-state latched output 5. Drives ±6 mA at 5 V; Hi-Z when OE is high.
16 4Q tri_state 3-state latched output 4. Drives ±6 mA at 5 V; Hi-Z when OE is high.
17 3Q tri_state 3-state latched output 3. Drives ±6 mA at 5 V; Hi-Z when OE is high.
18 2Q tri_state 3-state latched output 2. Drives ±6 mA at 5 V; Hi-Z when OE is high.
19 1Q tri_state 3-state latched output 1. Drives ±6 mA at 5 V; Hi-Z when OE is high.
20 VCC power_in Supply voltage (4.5 V to 5.5 V recommended, 7 V absolute max). Bypass with 0.1 µF close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74HCT573PWR
  • SN74HCT573PWRDW
  • SN74HCT573PWRDWR
  • SN74HCT573PWRDB
  • SN74HCT573PWRDBR
  • SN74HCT573PWRN
  • SN74HCT573PWRNS
  • SN74HCT573PWRNSR
  • SN74HCT573PWRFK
  • SN74HCT573PWRJ
  • SN74HCT573PWRW

CAD (KiCad official)

  • Symbol: SN74HCT573PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn74hct573pwr.step 267 KB You want the bare part, or you mark your own boards.
sn74hct573pwr-etched.step 2.9 MB You want the part with SN74HCT573PWR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 743 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 a628fd4b7163ff66, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF