8-bit serial-in, parallel-out shift register with an 8-bit D-type storage register and 3-state parallel outputs, in a SOIC-16 package. Separate shift-register (SRCLK) and storage-register (RCLK) clocks let you shift new data in without disturbing the outputs, then latch it in one edge. A direct SRCLR clears the shift register, OE tri-states QA-QH, and the QH' serial output chains multiple devices. The classic way to add cheap output pins to an MCU (LED banks, relays). Operates 2-6 V with up to ±6 mA per output.

Pinout

Pin	Name	Type	Function
1	QB	tri_state	Parallel 3-state output bit B from the 8-bit storage register. Drives up to 15 LSTTL loads (±6 mA typical at VCC = 4.5 V). Placed in high-impedance when OE is high.
2	QC	tri_state	Parallel 3-state output bit C from the 8-bit storage register. Placed in high-impedance when OE is high.
3	QD	tri_state	Parallel 3-state output bit D from the 8-bit storage register. Placed in high-impedance when OE is high.
4	QE	tri_state	Parallel 3-state output bit E from the 8-bit storage register. Placed in high-impedance when OE is high.
5	QF	tri_state	Parallel 3-state output bit F from the 8-bit storage register. Placed in high-impedance when OE is high.
6	QG	tri_state	Parallel 3-state output bit G from the 8-bit storage register. Placed in high-impedance when OE is high.
7	QH	tri_state	Parallel 3-state output bit H from the 8-bit storage register. Placed in high-impedance when OE is high.
8	GND	power_in	Ground reference (0 V) for the device.
9	QH'	output	Serial data output from the internal shift register (taken from the last shift stage, QH). Used for cascading multiple SN74HC595 devices. Not affected by OE (always driven).
10	SRCLR	input	Active-low shift-register clear. When low, asynchronously clears the 8-bit shift register; does not clear the storage register.
11	SRCLK	input	Shift-register clock input. On the rising edge, data at SER is shifted one position through QA'..QH' of the shift register.
12	RCLK	input	Storage-register (latch) clock input. On the rising edge, the shift-register contents are transferred in parallel to the storage register, updating outputs QA-QH.
13	OE	input	Active-low output enable. When low, the QA-QH parallel outputs are driven; when high, they enter the high-impedance state. Does not affect the serial cascade output QH'.
14	SER	input	Serial data input to the shift register. Sampled on the rising edge of SRCLK; shifted into stage A.
15	QA	tri_state	Parallel 3-state output bit A from the 8-bit storage register. Placed in high-impedance when OE is high.
16	VCC	power_in	Positive supply, 2 V to 6 V (recommended). Absolute maximum 7 V.

Key specifications

Parameter	Value
Type	8-bit shift register (SIPO)
Logic family	HC (high-speed CMOS)
Supply voltage (VCC)	2-6 V (7 V abs max)
Outputs	8 parallel 3-state (QA-QH) + serial QH'
Output drive	±6 mA per output
Clocking	Separate SRCLK (shift) + RCLK (latch)
Reset	Direct SRCLR (active low), OE tri-state
Package	SOIC-16
Body (L×W×H)	9.9 × 3.9 × 1.75 mm

Ordering variants

Same part, different packaging or reel option.

SN74HC595D (SOIC-16, tube)
SN74HC595DR (SOIC-16, tape & reel)

CAD (KiCad official)

Symbol: 74xx:74HC595
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (41 pp, sha256 215816945704e561, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude) — every pin and dimension is cited to a datasheet page; refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF