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SN74HC594D
Public Unreviewedby Ray
lingxingic Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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markdownSN74HC594D
lingxingic · Shifting Register · SOP-16
SN74HC594D from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | output | Parallel data output bit 1 from the 8-bit storage register. Driven from the storage-register flip-flop, updated on the rising edge of STCP when STR is HIGH. |
| 2 | Q2 | output | Parallel data output bit 2 from the 8-bit storage register. |
| 3 | Q3 | output | Parallel data output bit 3 from the 8-bit storage register. |
| 4 | Q4 | output | Parallel data output bit 4 from the 8-bit storage register. |
| 5 | Q5 | output | Parallel data output bit 5 from the 8-bit storage register. |
| 6 | Q6 | output | Parallel data output bit 6 from the 8-bit storage register. |
| 7 | Q7 | output | Parallel data output bit 7 (MSB) from the 8-bit storage register. |
| 8 | GND | power_in | Ground reference (0 V) for the device. |
| 9 | Q7S | output | Serial data output from the last stage (stage 7) of the shift register. Used for cascading multiple 594 devices; drives the DS input of the next stage. |
| 10 | SHR | input | Shift-register asynchronous reset, active LOW. Clears all 8 shift-register flip-flops when driven LOW; does not affect the storage register. |
| 11 | SHCP | input | Shift-register clock input. Data on DS is loaded into shift-register stage 0 and existing data is advanced one stage on the LOW-to-HIGH transition. |
| 12 | STCP | input | Storage-register clock input. On the LOW-to-HIGH transition (with STR HIGH), the current shift-register contents are transferred in parallel into the storage register and driven onto Q0-Q7. |
| 13 | STR | input | Storage-register asynchronous reset, active LOW. Clears the 8-bit storage register (Q0-Q7 driven LOW) when driven LOW; does not affect the shift register. |
| 14 | DS | input | Serial data input. Sampled into shift-register stage 0 on the rising edge of SHCP. |
| 15 | Q0 | output | Parallel data output bit 0 (LSB) from the 8-bit storage register. |
| 16 | VCC | power_in | Positive supply voltage. 2 V to 6 V for SN74HC594; 4.5 V to 5.5 V for SN74HCT594. Bypass locally with a 100 nF ceramic capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
SN74HC594DDSN74HC594DNSN74HC594DPWR
CAD (KiCad official)
- Symbol:
SN74HC594D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (23 pp, sha256
6701152582d6d4fa, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).