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SN74HC573APWR

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by Ray

Texas Instruments Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN74HC573APWR

Texas Instruments · Latches · TSSOP-20

SN74HC573APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable. When OE is low, the 3-state Q outputs are enabled; when high, the outputs are Hi-Z.
2 1D input Data input 1 to the D-type latch. Captured to 1Q when LE is high; latched on LE falling edge.
3 2D input Data input 2 to the D-type latch. Captured to 2Q when LE is high; latched on LE falling edge.
4 3D input Data input 3 to the D-type latch. Captured to 3Q when LE is high; latched on LE falling edge.
5 4D input Data input 4 to the D-type latch. Captured to 4Q when LE is high; latched on LE falling edge.
6 5D input Data input 5 to the D-type latch. Captured to 5Q when LE is high; latched on LE falling edge.
7 6D input Data input 6 to the D-type latch. Captured to 6Q when LE is high; latched on LE falling edge.
8 7D input Data input 7 to the D-type latch. Captured to 7Q when LE is high; latched on LE falling edge.
9 8D input Data input 8 to the D-type latch. Captured to 8Q when LE is high; latched on LE falling edge.
10 GND power_in Ground reference (0 V). Connect to system ground.
11 LE input Latch enable input. When high, Q outputs are transparent to D inputs; on the falling edge the data is latched.
12 8Q tri_state 3-state latched data output 8. Reflects 8D when LE is high and OE is low; Hi-Z when OE is high.
13 7Q tri_state 3-state latched data output 7. Reflects 7D when LE is high and OE is low; Hi-Z when OE is high.
14 6Q tri_state 3-state latched data output 6. Reflects 6D when LE is high and OE is low; Hi-Z when OE is high.
15 5Q tri_state 3-state latched data output 5. Reflects 5D when LE is high and OE is low; Hi-Z when OE is high.
16 4Q tri_state 3-state latched data output 4. Reflects 4D when LE is high and OE is low; Hi-Z when OE is high.
17 3Q tri_state 3-state latched data output 3. Reflects 3D when LE is high and OE is low; Hi-Z when OE is high.
18 2Q tri_state 3-state latched data output 2. Reflects 2D when LE is high and OE is low; Hi-Z when OE is high.
19 1Q tri_state 3-state latched data output 1. Reflects 1D when LE is high and OE is low; Hi-Z when OE is high.
20 VCC power_in Positive supply voltage, 2 V to 6 V (nominal 5 V). Bypass locally to GND with a 0.1 uF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74HC573APWR
  • SN74HC573APWRDB
  • SN74HC573APWRDBR
  • SN74HC573APWRDW
  • SN74HC573APWRDWR
  • SN74HC573APWRN
  • SN74HC573APWRJ
  • SN74HC573APWRW
  • SN74HC573APWRFK

CAD (KiCad official)

  • Symbol: SN74HC573APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 6cc6ba17b27ea9a4, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF