Two independent 4-bit binary ripple counters in one SOIC-14. Each counter advances on the falling edge of its clock and presents the count on four outputs (QA-QD, QA is the LSB), with an active-high clear to reset to zero. Feed one counter's QD into the other's clock and they cascade into an 8-bit counter (0-255); chain more packages for wider counts. It is the compact way to divide a clock, generate addresses, or time events. Runs 2-6 V. The pinout matches the 74LS393; this page ships the KiCad 74LS393 symbol, which is pin-identical.

Pinout

Pin	Name	Type	Function
1	1CLK	input	Counter 1 clock input. Counter 1 advances on the high-to-low (falling-edge) transition of this input. CMOS-level input, 2 V to 6 V logic swing; typical clock frequency 31 MHz at VCC=4.5 V.
2	1CLR	input	Counter 1 asynchronous clear input, active high. When held high, Q1A-Q1D are forced low regardless of 1CLK. Minimum high pulse width ~16 ns at VCC=4.5 V.
3	1QA	output	Counter 1 stage A (LSB) output. Toggles on each falling edge of 1CLK; divides input clock by 2. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
4	1QB	output	Counter 1 stage B output. Toggles on each falling edge of 1QA; divides 1CLK by 4. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
5	1QC	output	Counter 1 stage C output. Toggles on each falling edge of 1QB; divides 1CLK by 8. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
6	1QD	output	Counter 1 stage D (MSB) output. Toggles on each falling edge of 1QC; divides 1CLK by 16. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
7	GND	power_in	Ground reference (0 V). Return path for VCC current.
8	2QD	output	Counter 2 stage D (MSB) output. Toggles on each falling edge of 2QC; divides 2CLK by 16. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
9	2QC	output	Counter 2 stage C output. Toggles on each falling edge of 2QB; divides 2CLK by 8. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
10	2QB	output	Counter 2 stage B output. Toggles on each falling edge of 2QA; divides 2CLK by 4. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
11	2QA	output	Counter 2 stage A (LSB) output. Toggles on each falling edge of 2CLK; divides input clock by 2. Push-pull CMOS output, ±4 mA drive at VCC=5 V.
12	2CLR	input	Counter 2 asynchronous clear input, active high. When held high, Q2A-Q2D are forced low regardless of 2CLK. Minimum high pulse width ~16 ns at VCC=4.5 V.
13	2CLK	input	Counter 2 clock input. Counter 2 advances on the high-to-low (falling-edge) transition of this input. CMOS-level input, 2 V to 6 V logic swing.
14	VCC	power_in	Positive supply. Recommended 2 V to 6 V (5 V nominal). Bypass to GND with 0.1 µF (and optional 1 µF) placed close to the pin.

Key specifications

Parameter	Value
Type	Dual 4-bit binary counter
Counters	2 independent (4-bit each)
Clock	negative-edge triggered
Reset	active-high clear per counter
Cascade	QD to next CLK (8-bit and beyond)
Logic family	HC (high-speed CMOS)
Supply voltage	2-6 V
Package	SOIC-14

Ordering variants

Same part, different packaging or reel option.

SN74HC393D (SOIC-14, tube)
SN74HC393DR (SOIC-14, tape & reel)

CAD (KiCad official)

Symbol: 74xx:74LS393 (pin-compatible with 74HC393)
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 aa77c46be80d7142, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF