Eight transparent D-type latches with 3-state outputs in a SOIC-20. While the latch-enable (LE) pin is high the outputs follow the D inputs (transparent); take LE low and each latch holds the last value. A separate active-low output-enable (/OE) puts all eight outputs into high-impedance for bus sharing. The classic use is de-multiplexing an address/data bus (as on the 8051 and 8085), latching the low address byte while the same pins later carry data. Runs 2-6 V.

Pinout

Pin	Name	Type	Function
1	OE	input	Active-low output enable. When low, the Q outputs are actively driven; when high, all Q outputs are placed in the high-impedance (3-state) state. Does not affect the stored latch state.
2	1Q	tri_state	3-state output for latch channel 1. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
3	1D	input	Data input for latch channel 1. Passes to 1Q while LE is high; captured on LE falling edge.
4	2D	input	Data input for latch channel 2. Passes to 2Q while LE is high; captured on LE falling edge.
5	2Q	tri_state	3-state output for latch channel 2. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
6	3Q	tri_state	3-state output for latch channel 3. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
7	3D	input	Data input for latch channel 3. Passes to 3Q while LE is high; captured on LE falling edge.
8	4D	input	Data input for latch channel 4. Passes to 4Q while LE is high; captured on LE falling edge.
9	4Q	tri_state	3-state output for latch channel 4. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
10	GND	power_in	Ground reference (0 V) for the device.
11	LE	input	Latch enable, common to all eight latches. When high, Q outputs transparently follow D inputs; when driven low, the D-input state at the falling edge is latched at the outputs. Setup time 15 ns and hold time 13 ns at 4.5 V.
12	5Q	tri_state	3-state output for latch channel 5. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
13	5D	input	Data input for latch channel 5. Passes to 5Q while LE is high; captured on LE falling edge.
14	6D	input	Data input for latch channel 6. Passes to 6Q while LE is high; captured on LE falling edge.
15	6Q	tri_state	3-state output for latch channel 6. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
16	7Q	tri_state	3-state output for latch channel 7. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
17	7D	input	Data input for latch channel 7. Passes to 7Q while LE is high; captured on LE falling edge.
18	8D	input	Data input for latch channel 8. Passes to 8Q while LE is high; captured on LE falling edge.
19	8Q	tri_state	3-state output for latch channel 8. Drives ±6 mA at 5 V; enters Hi-Z when OE is high.
20	VCC	power_in	Positive supply. Recommended operating range 2 V to 6 V (absolute max 7 V). Bypass with a local 0.1 µF ceramic to GND.

Key specifications

Parameter	Value
Type	Octal transparent D latch, 3-state
Latches	8
Latch enable	LE (transparent high, hold low)
Output enable	/OE (active-low, Hi-Z)
Logic family	HC (high-speed CMOS)
Supply voltage	2-6 V
Package	SOIC-20
Body (L×W×H)	12.8 × 7.5 × 2.35 mm

Ordering variants

Same part, different packaging or reel option.

SN74HC373DW (SOIC-20, tube)
SN74HC373DWR (SOIC-20, tape & reel)

CAD (KiCad official)

Symbol: 74xx:74HC373
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20W (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 09faaa55733b1ac6, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF