An 8-bit addressable latch in high-speed CMOS, SOIC-16, a flexible little memory. A 3-bit address (S0-S2) selects one of eight internal latches, and the data pin (D) writes that one latch while the other seven hold their values, so a microcontroller sets or clears any single output bit without disturbing the rest. The same part also works as a 1-of-8 demultiplexer or an 8-bit addressable memory, and a clear input resets all outputs. It is a compact way to expand output bits or build a set of independently controlled flags. Runs 2-6 V.

Pinout

Pin	Name	Type	Function
1	S0	input	Address select input, bit 0 (LSB). With S2/S1/S0 selects one of the eight internal latches Q0..Q7 per Table 7-2. CMOS input, VIH = 3.15 V at VCC = 4.5 V.
2	S1	input	Address select input, bit 1. Selects the target latch together with S2 and S0.
3	S2	input	Address select input, bit 2 (MSB). Selects the target latch together with S1 and S0.
4	Q0	output	Active-high latch output 0. Follows D when addressed and G is low; otherwise holds its previous state. Forced low when CLR is low. Push-pull CMOS, ±4 mA drive at VCC = 5 V.
5	Q1	output	Active-high latch output 1. Same electrical behavior as Q0.
6	Q2	output	Active-high latch output 2. Same electrical behavior as Q0.
7	Q3	output	Active-high latch output 3. Same electrical behavior as Q0.
8	GND	power_in	Ground reference (0 V). Must be tied to the system GND rail.
9	Q4	output	Active-high latch output 4. Same electrical behavior as Q0.
10	Q5	output	Active-high latch output 5. Same electrical behavior as Q0.
11	Q6	output	Active-high latch output 6. Same electrical behavior as Q0.
12	Q7	output	Active-high latch output 7. Same electrical behavior as Q0.
13	D	input	Serial data input. Value latched into the addressed output while G is low (addressable-latch mode) or routed to the addressed output in 1-of-8 demultiplex mode.
14	G	input	Active-low enable (write strobe). When low with CLR high, the addressed latch tracks D; when high, all latches hold their previous state (memory mode). Rising edge captures D with tsu = 15 ns, th = 5 ns at VCC = 4.5 V.
15	CLR	input	Active-low asynchronous clear. Forces all Q0..Q7 outputs low regardless of address/data inputs. Minimum low pulse width 16 ns at VCC = 4.5 V.
16	VCC	power_in	Positive supply, 2 V to 6 V (5 V nominal). Decouple locally with 0.1 µF close to the pin per datasheet Section 8. ICC ≤ 80 µA at VCC = 6 V (SN74).

Key specifications

Parameter	Value
Type	8-bit addressable latch
Latches	8 (individually addressed)
Address	3-bit (S0-S2)
Data	D writes the selected latch
Modes	addressable latch / demux / memory
Reset	clear (CLR)
Logic family	HC (high-speed CMOS)
Supply voltage	2-6 V
Package	SOIC-16

Ordering variants

Same part, different packaging or reel option.

SN74HC259D (SOIC-16, tube)
SN74HC259DR (SOIC-16, tape & reel)

CAD (KiCad official)

Symbol: 74xx:74LS259 (pin-compatible with 74HC259)
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 bf1d352862715b29, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF