SN74HC166DR
Public Unreviewedby Ray
Texas Instruments Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownSN74HC166DR
Texas Instruments · Shifting Register · SOIC-16
SN74HC166DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SER | input | Serial data input. Shifted into the register on the rising edge of CLK when SH/LD is high. |
| 2 | A | input | Parallel input A. Loaded into shift-register stage A on the next clock rising edge when SH/LD is low. |
| 3 | B | input | Parallel input B. Loaded into shift-register stage B on the next clock rising edge when SH/LD is low. |
| 4 | C | input | Parallel input C. Loaded into shift-register stage C on the next clock rising edge when SH/LD is low. |
| 5 | D | input | Parallel input D. Loaded into shift-register stage D on the next clock rising edge when SH/LD is low. |
| 6 | CLK INH | input | Clock inhibit input. When held high, inhibits clocking; should transition high only while CLK is high to avoid glitches. |
| 7 | CLK | input | Clock input, positive-edge triggered. Shifts or loads the register on the rising edge depending on SH/LD. |
| 8 | GND | power_in | Ground reference (0 V). |
| 9 | CLR | input | Active-low asynchronous clear. Overrides all other inputs, including CLK, and resets all flip-flops to zero. |
| 10 | E | input | Parallel input E. Loaded into shift-register stage E on the next clock rising edge when SH/LD is low. |
| 11 | F | input | Parallel input F. Loaded into shift-register stage F on the next clock rising edge when SH/LD is low. |
| 12 | G | input | Parallel input G. Loaded into shift-register stage G on the next clock rising edge when SH/LD is low. |
| 13 | QH | output | Serial data output from the last (H) shift-register stage. Drives ±4 mA at VCC = 5 V. |
| 14 | H | input | Parallel input H. Loaded into shift-register stage H on the next clock rising edge when SH/LD is low. |
| 15 | SH/LD | input | Shift/load mode select. High enables serial shifting from SER; low enables synchronous parallel load from A-H on the next CLK rising edge. |
| 16 | VCC | power_in | Positive supply rail, 2 V to 6 V (5 V nominal). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
SN74HC166DRDSN74HC166DRSN74HC166DRDBSN74HC166DRDBRSN74HC166DRNSN74HC166DRNSSN74HC166DRNSRSN74HC166DRPWSN74HC166DRPWRSN74HC166DRJSN74HC166DRFK
CAD (KiCad official)
- Symbol:
SN74HC166DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
sn74hc166dr.step |
217 KB | You want the bare part, or you mark your own boards. |
sn74hc166dr-etched.step |
2.6 MB | You want the part with SN74HC166DR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 647 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
6e3f10dd0226bea6, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).