An 8-bit parallel-in, serial-out shift register in high-speed CMOS, SOIC-16, the mirror image of the 74HC595: it reads eight inputs into a microcontroller over three wires. Pulse SH/LD low and the eight parallel inputs (A-H) latch; then each clock shifts them out MSB-first on QH, with a complementary /QH also available. A serial input (SER) and clock-inhibit let you cascade several devices to read 16, 24, or more inputs on the same three pins. Runs 2-6 V.

Pinout

Pin	Name	Type	Function
1	SH/LD	input	Shift or Load input (active-low load). When high, data is shifted on the rising edge of CLK. When low, data is asynchronously loaded from the parallel inputs A-H, independent of CLK/CLK INH/SER levels.
2	CLK	input	Clock input. On a low-to-high transition (with SH/LD high and CLK INH low) data is shifted one bit toward the QH serial output.
3	E	input	Parallel data input E. Loaded into stage E of the register while SH/LD is low.
4	F	input	Parallel data input F. Loaded into stage F of the register while SH/LD is low.
5	G	input	Parallel data input G. Loaded into stage G of the register while SH/LD is low.
6	H	input	Parallel data input H (the last stage before the QH serial output). Loaded into stage H of the register while SH/LD is low.
7	/QH	output	Complementary serial output - the logical inverse of the last-stage (H) flip-flop. Drives ±4 mA at VCC = 5 V; up to 10 LSTTL loads.
8	GND	power_in	Ground reference (0 V) for the device.
9	QH	output	Serial output - the state of the last-stage (H) flip-flop. Data shifted through the register appears here bit-by-bit on each CLK rising edge. Drives ±4 mA at VCC = 5 V; up to 10 LSTTL loads.
10	SER	input	Serial data input. Feeds the first stage (A) of the register when SH/LD is high; sampled on the rising edge of CLK.
11	A	input	Parallel data input A (the first stage, adjacent to SER). Loaded into stage A of the register while SH/LD is low.
12	B	input	Parallel data input B. Loaded into stage B of the register while SH/LD is low.
13	C	input	Parallel data input C. Loaded into stage C of the register while SH/LD is low.
14	D	input	Parallel data input D. Loaded into stage D of the register while SH/LD is low.
15	CLK INH	input	Clock inhibit. When high, no shifting occurs; functionally interchangeable with CLK (either input can serve as clock while the other is held low). Must be transitioned high only while CLK is high to avoid a double-clock.
16	VCC	power_in	Positive supply, 2 V to 6 V (5 V nominal). Absolute maximum 7 V. Bypass with a local ceramic capacitor to GND.

Key specifications

Parameter	Value
Type	8-bit PISO shift register
Load	parallel (SH/LD low latches A-H)
Serial out	QH + complementary /QH
Cascade	SER input + CLK INH
Shift direction	MSB first
Logic family	HC (high-speed CMOS)
Supply voltage	2-6 V
Package	SOIC-16

Ordering variants

Same part, different packaging or reel option.

SN74HC165D (SOIC-16, tube)
SN74HC165DR (SOIC-16, tape & reel)

CAD (KiCad official)

Symbol: 74xx:74HC165
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (37 pp, sha256 517390062d4006fc, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF