SN74HC161DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLR	input	Active-low asynchronous clear. Driving CLR low forces all four Q outputs (QA-QD) low regardless of CLK, LOAD, or enable states.
2	CLK	input	Buffered clock input. All four internal D/T flip-flops are triggered on the rising (positive-going) edge of CLK. Max clock frequency is ~25 MHz at Vcc=4.5 V.
3	A	input	Parallel data input A (LSB of the 4-bit preset value). Loaded synchronously into the QA flip-flop on the rising edge of CLK when LOAD is low.
4	B	input	Parallel data input B. Loaded synchronously into the QB flip-flop on the rising edge of CLK when LOAD is low.
5	C	input	Parallel data input C. Loaded synchronously into the QC flip-flop on the rising edge of CLK when LOAD is low.
6	D	input	Parallel data input D (MSB of the 4-bit preset value). Loaded synchronously into the QD flip-flop on the rising edge of CLK when LOAD is low.
7	ENP	input	Count enable (P). Must be high, together with ENT, to enable counting on the next CLK rising edge. Transitions on ENP are allowed regardless of CLK state.
8	GND	power_in	Ground reference (0 V) for the device.
9	LOAD	input	Active-low synchronous parallel-load input. A low level disables counting and forces QA-QD to match the A-D inputs on the next rising edge of CLK.
10	ENT	input	Count enable (T). Must be high, together with ENP, to enable counting; ENT is also fed forward to gate the RCO output. Transitions on ENT are allowed regardless of CLK state.
11	QD	output	Counter output bit D (MSB). Push-pull CMOS output capable of driving ±4 mA at Vcc=5 V (up to 10 LSTTL loads).
12	QC	output	Counter output bit C. Push-pull CMOS output capable of driving ±4 mA at Vcc=5 V.
13	QB	output	Counter output bit B. Push-pull CMOS output capable of driving ±4 mA at Vcc=5 V.
14	QA	output	Counter output bit A (LSB). Push-pull CMOS output capable of driving ±4 mA at Vcc=5 V.
15	RCO	output	Ripple-carry output. Produces a high-level pulse (gated by ENT) when the count reaches its maximum value (15, with QA high), used to cascade successive counter stages for n-bit synchronous counting.
16	VCC	power_in	Positive supply voltage, 2 V to 6 V recommended operating range (absolute max 7 V). Typical Icc is 80 µA max for the 74HC variant.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

SN74HC161DRD
SN74HC161DR
SN74HC161DRDT
SN74HC161DRN
SN74HC161DRNSR
SN74HC161DRPW
SN74HC161DRPWR
SN74HC161DRPWT
SN74HC161DRJ
SN74HC161DRW
SN74HC161DRFK

CAD (KiCad official)

Symbol: SN74HC161DR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 58fced3e842dd1c0, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF