SN74GTL2003PWR from Texas Instruments, in a TSSOP-20(4.4x6.5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground reference (0 V).
2	SREF	passive	Source of the reference transistor. Used with DREF/GREF to bias the pass transistors; VSREF operating range 0-5.5 V (VSREF = VDREF - 1.5 V recommended for best level-shifting).
3	S1	bidirectional	Channel 1 LVTTL/TTL source port (low-voltage side of the pass transistor). Operating voltage 0-5.5 V.
4	S2	bidirectional	Channel 2 LVTTL/TTL source port. Operating voltage 0-5.5 V.
5	S3	bidirectional	Channel 3 LVTTL/TTL source port. Operating voltage 0-5.5 V.
6	S4	bidirectional	Channel 4 LVTTL/TTL source port. Operating voltage 0-5.5 V.
7	S5	bidirectional	Channel 5 LVTTL/TTL source port. Operating voltage 0-5.5 V.
8	S6	bidirectional	Channel 6 LVTTL/TTL source port. Operating voltage 0-5.5 V.
9	S7	bidirectional	Channel 7 LVTTL/TTL source port. Operating voltage 0-5.5 V.
10	S8	bidirectional	Channel 8 LVTTL/TTL source port. Operating voltage 0-5.5 V.
11	D8	bidirectional	Channel 8 GTL/GTL+ drain port (high-voltage side of the pass transistor).
12	D7	bidirectional	Channel 7 GTL/GTL+ drain port.
13	D6	bidirectional	Channel 6 GTL/GTL+ drain port.
14	D5	bidirectional	Channel 5 GTL/GTL+ drain port.
15	D4	bidirectional	Channel 4 GTL/GTL+ drain port.
16	D3	bidirectional	Channel 3 GTL/GTL+ drain port.
17	D2	bidirectional	Channel 2 GTL/GTL+ drain port.
18	D1	bidirectional	Channel 1 GTL/GTL+ drain port.
19	DREF	passive	Drain of the reference transistor. Tie directly to GREF and pull up to the reference voltage through a 200-kΩ resistor. Operating range 0-5.5 V.
20	GREF	passive	Gate of the reference transistor and common gate node for all Sn/Dn pass transistors. Tie directly to DREF and pull up to the reference voltage through a 200-kΩ resistor. Operating range 0-5.5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20(4.4x6.5)
Category	Logic
Pins	20

Ordering variants

Same part, different packaging or reel option.

SN74GTL2003PWR
SN74GTL2003PWRRKS
SN74GTL2003PWRRKSR

CAD (KiCad official)

Symbol: SN74GTL2003PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20(4.4x6.5) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sn74gtl2003pwr.step`	267 KB	You want the bare part, or you mark your own boards.
`sn74gtl2003pwr-etched.step`	3.3 MB	You want the part with `SN74GTL2003PWR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 830 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (30 pp, sha256 d59069f5fece5173, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF