Converts one single-ended LVTTL/LVCMOS logic input (D) into a differential LVDS pair (Y, Z) for driving a controlled-impedance line at high speed with low noise and low power. LVDS swings only a few hundred millivolts around a common-mode point, so it carries signals past 400 Mbps while radiating little and rejecting common-mode pickup, which suits it to backplanes, clock distribution, and long board traces. Runs from a single 3.3 V supply. A single-channel building block for point-to-point differential links.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Supply voltage. Recommended 2.4V to 3.6V (3.3V nominal). Driver output is high-impedance when VCC < 1.5V.
2	D	input	LVTTL input signal. VIH ≥ 2V, VIL ≤ 0.8V; 5V tolerant. Drives the differential Y/Z output pair.
4	GND	power_in	Ground reference for the device.
7	Y	output	Differential LVDS non-inverting output. Pair with Z drives a 100Ω terminated differential line with
8	Z	output	Differential LVDS inverting output. Pair with Y drives a 100Ω terminated differential line with

Key specifications

Parameter	Value
Type	Single LVDS line driver
Input	LVTTL / LVCMOS (D)
Output	Differential LVDS (Y, Z)
Data rate	> 400 Mbps
Standard	TIA/EIA-644 (LVDS)
Supply	3.3 V
Package	SOIC-8

Ordering variants

Same part, different packaging or reel option.

SN65LVDS1D (SOIC-8)
SN65LVDS1DBV (SOT-23-5)

CAD (KiCad official)

Symbol: Interface:SN65LVDS1D (KiCad official)
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (44 pp, sha256 2830b1f2b732d16f, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF