SLM8254AAV from SOLA IC, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COP	output	Charge-control FET gate drive terminal (Nch open-drain output). Drives the external charge-path N-MOSFET; goes high (through external pull-up) to disable charging on overcharge or 0V-charge inhibit.
2	VMP	input	Voltage sense terminal between VC1 and VMP, used as the overcurrent-3 (charger over-current / charger-detect) detection input. Internally tied to VDD via ~1 MΩ (R_VMD) and to VSS via ~900 kΩ (R_VMS).
3	DOP	output	Discharge-control FET gate drive terminal (CMOS output, VSS↔VDD). Drives the external discharge-path N-MOSFET; goes low to disable discharge on overdischarge or overcurrent 1/2/3.
4	VINI	input	Voltage sense terminal between VSS and VINI, used as the overcurrent-1 and overcurrent-2 detection input. Connect to the pack's V- (load) side through the sense resistance of the series FETs.
5	CDT	passive	Delay-capacitor terminal for overdischarge detection delay (t_DL) and overcurrent-1 detection delay (t_IOV1). Typical external capacitor 0.1 µF sets t_DL ≈ 100 ms, t_IOV1 ≈ 10 ms.
6	CCT	passive	Delay-capacitor terminal for overcharge detection delay (t_CU). Typical external capacitor 0.1 µF sets t_CU ≈ 1 s.
7	VSS	power_in	Negative supply input; connects to the negative terminal of the bottom cell (cell 4 in 4-series mode).
8	NC	unconnected	No connection.
9	NC	unconnected	No connection.
10	SEL	input	3/4-series select input. Tie to VSS for 3-cell mode, tie to VDD for 4-cell mode. V_SELH ≥ VDD×0.8, V_SELL ≤ VDD×0.2.
11	CTL	input	Control input to enable/disable the charge and discharge FETs (COP and DOP). V_CTLH ≥ VDD×0.8, V_CTLL ≤ VDD×0.2.
12	VC4	input	Sense pin: negative terminal of cell 3 / positive terminal of cell 4. Used for per-cell overcharge and overdischarge detection.
13	VC3	input	Sense pin: negative terminal of cell 2 / positive terminal of cell 3. Used for per-cell overcharge and overdischarge detection.
14	VC2	input	Sense pin: negative terminal of cell 1 / positive terminal of cell 2. Used for per-cell overcharge and overdischarge detection.
15	VC1	input	Positive terminal sense pin of cell 1 (the top-most cell). Used together with VDD for cell-1 voltage detection.
16	VDD	power_in	Positive supply input; connects to the positive terminal of cell 1 (the pack's +) via a series resistor. Absolute max VSS+26 V; operating VDD-VSS = 3 V to 24 V.

Key specifications

Parameter	Value
Manufacturer	SOLA IC
Package	TSSOP-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

SLM8254AAV
SLM8254AAVAAF
SLM8254AAVAAN
SLM8254AAVAAQ

CAD (KiCad official)

Symbol: SLM8254AAV
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`slm8254aav.step`	205 KB	You want the bare part, or you mark your own boards.
`slm8254aav-etched.step`	2.3 MB	You want the part with `SLM8254AAV` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 588 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SOLA IC datasheet (22 pp, sha256 df2f7926e9b67b0b, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF