SIT490EESA from SIT, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Positive supply input, 4.5 V ≤ VCC ≤ 5.5 V (absolute max +7 V). Typical supply current ICC = 220 µA (max 400 µA) with DI = 0 or VCC.
2	RO	output	Receiver output. Outputs logic high when the differential receiver input (A−B) ≥ −10 mV, and logic low when (A−B) ≤ −200 mV. Fail-safe high when inputs are open or shorted. VOH ≥ VCC−1.5 V at IOUT = −4 mA; VOL ≤ 0.4 V at IOUT = +4 mA.
3	DI	input	Driver data input. A logic low on DI forces Y low and Z high; a logic high on DI forces Y high and Z low. VIH ≥ 2.0 V, VIL ≤ 0.8 V, input leakage ±2 µA.
4	GND	power_in	Device ground reference. All voltages are referenced to this pin.
5	Y	output	Non-inverting (in-phase) driver output for the RS-485/RS-422 bus. Differential output magnitude 1.5-VCC V into a 27 Ω load (2.0-VCC V into 50 Ω). Short-circuit protected 35-250 mA. ±15 kV HBM ESD protection.
6	Z	output	Inverting driver output for the RS-485/RS-422 bus. Complementary to Y. Short-circuit protected 35-250 mA. ±15 kV HBM ESD protection.
7	B	input	Inverting receiver differential input from the RS-485/RS-422 bus. Common-mode range −7 V to +12 V, 1/8-unit-load input impedance (RIN ≥ 96 kΩ). Absolute max −8 V to +13 V. ±15 kV HBM ESD protection.
8	A	input	Non-inverting receiver differential input from the RS-485/RS-422 bus. Common-mode range −7 V to +12 V, 1/8-unit-load input impedance (RIN ≥ 96 kΩ). Absolute max −8 V to +13 V. ±15 kV HBM ESD protection.

Key specifications

Parameter	Value
Manufacturer	SIT
Package	SOP-8
Category	Interface
Pins	8

Ordering variants

Same part, different packaging or reel option.

SIT490EESA
SIT490EESAEPA
SIT490EESAEUA

CAD (KiCad official)

Symbol: SIT490EESA
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sit490eesa.step`	122 KB	You want the bare part, or you mark your own boards.
`sit490eesa-etched.step`	2.1 MB	You want the part with `SIT490EESA` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 516 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SIT datasheet (9 pp, sha256 a23c5cb34e7cf8bc, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF