SIT1040T from SIT, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TXD	input	Transmit data input from the CAN protocol controller. Drives the bus dominant when low and recessive when high. 3.3 V / 5 V logic compatible; VIH ≥ 2 V, VIL ≤ 0.8 V. Internal pull-up leaves TXD in the recessive state when floating (TXD_O = H).
2	GND	power_in	Ground / device reference. All voltages are referenced to this pin.
3	VCC	power_in	Supply voltage input, nominal 5 V (operating range 4.5 V to 5.5 V, absolute max -0.3 V to +6 V). Should be decoupled to GND with a local bypass capacitor.
4	RXD	output	Receive data output to the CAN protocol controller. Reports the bus state: LOW when the bus is dominant, HIGH when recessive. Push-pull output; VOH ≥ 4 V @ IO = -2 mA, VOL ≤ 0.4 V @ IO = 2 mA.
5	SPLIT	output	Common-mode stabilization output, nominally VCC/2 (0.3·VCC to 0.7·VCC for
6	CANL	bidirectional	Low-level CAN bus line. Driven low in the dominant state and biased to ~VCC/2 in the recessive state. Rated -40 V to +40 V continuous, ±200 V transient; ±8 kV HBM ESD.
7	CANH	bidirectional	High-level CAN bus line. Driven high in the dominant state and biased to ~VCC/2 in the recessive state. Rated -40 V to +40 V continuous, ±200 V transient; ±8 kV HBM ESD.
8	STB	input	Standby mode control input. STB = 0 selects normal (high-speed) operation; STB = 1 selects low-power standby (~5 µA typical) with bus wake-up capability. VIH ≥ 2.0 V, VIL ≤ 0.8 V.

Key specifications

Parameter	Value
Manufacturer	SIT
Package	SO-8
Category	Interface
Pins	8

Ordering variants

Same part, different packaging or reel option.

SIT1040TT

CAD (KiCad official)

Symbol: SIT1040T
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sit1040t.step`	122 KB	You want the bare part, or you mark your own boards.
`sit1040t-etched.step`	1.6 MB	You want the part with `SIT1040T` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 422 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SIT datasheet (17 pp, sha256 8da36b80cd179b04, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF