component
SG3525AP013TR
Public Made by Adomby adom
STMicroelectronics AC-DC Controllers and Regulators, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSG3525AP013TR
STMicroelectronics · AC-DC Controllers and Regulators · SOIC-16
SG3525AP013TR from STMicroelectronics, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV. INPUT | input | Inverting input of the internal error amplifier. Common-mode input range includes the 5.1 V reference so external divider resistors are not required. Vos typ 0.5 mV, Ib typ 1 µA. |
| 2 | N.I. INPUT | input | Non-inverting input of the internal error amplifier. Typically tied to the VREF (pin 16) divider providing the regulation setpoint. CMR typ 75 dB. |
| 3 | SYNC | bidirectional | Oscillator sync terminal. Bidirectional: allows multiple SG3525A units to be slaved together or the device to be synchronized to an external system clock. Sync threshold typ 2 V, sync input current typ 1 mA at 3.5 V. |
| 4 | OSC. OUTPUT | output | Buffered oscillator clock output. Provides a system clock signal (amplitude typ 3.5 V) that can drive external logic or additional SG3525A devices. |
| 5 | CT | passive | Oscillator timing capacitor terminal. Connect timing capacitor (0.001 µF to 0.1 µF) from CT to ground. With RT sets the oscillator frequency (100 Hz-400 kHz operating range). Charge current limit 5 mA. |
| 6 | RT | passive | Oscillator timing resistor terminal. Connect timing resistor (2 kΩ to 150 kΩ) from RT to ground. Together with CT sets the oscillator frequency per f ≈ 1/(CT(0.7·RT + 3·RD)). |
| 7 | DISCHARGE | passive | Dead-time / discharge terminal. A resistor (RD, 0-500 Ω) placed between RT (pin 6) and DISCHARGE (pin 7) sets the timing-capacitor discharge current, giving programmable dead-time between the two outputs. |
| 8 | SOFT-START | passive | Soft-start capacitor terminal. An internal ~50 µA current source charges the external capacitor to progressively enable the PWM after start-up. Also discharged during shutdown for soft recycle. |
| 9 | COMP | output | Error-amplifier output / PWM comparator input (compensation node). Frequency-compensation network is tied here. Output high ≥3.8 V, output low ≤0.5 V; DC open-loop gain typ 75 dB. |
| 10 | SHUTDOWN | input | Pulse-by-pulse shutdown input. Threshold typ 0.8 V (0.6-1.0 V). When asserted (>threshold, VSS = 2.5 V typical drive) the PWM latch immediately turns both outputs off and discharges the soft-start capacitor. Shutdown delay typ 0.2 µs. |
| 11 | OUTPUT A | output | Totem-pole PWM driver output A. Alternates with OUTPUT B at half the oscillator frequency. Capable of sourcing/sinking >200 mA (400 mA peak). Rise/fall typ 100/50 ns into 1 nF. |
| 12 | GROUND | power_in | Signal and power ground reference for all internal circuitry. |
| 13 | VC | power_in | Collector (driver) supply for the totem-pole output stages. Operating range 4.5 V to 35 V (absolute max 40 V). Bypass locally with a low-ESR capacitor. |
| 14 | OUTPUT B | output | Totem-pole PWM driver output B, complementary to OUTPUT A with programmable dead-time between them. Source/sink capability >200 mA (400 mA peak). |
| 15 | +VI | power_in | Main IC supply voltage. Operating range 8 V to 35 V (absolute max 40 V). Undervoltage lockout keeps outputs off until Vcomp and Vss thresholds (6-8 V, typ 7 V) are exceeded, with ~500 mV hysteresis. Standby current typ 14 mA. |
| 16 | VREF | power_out | Trimmed 5.1 V ±1 % reference output (5.05-5.15 V at Tj=25 °C for SG2525A; 5.0-5.2 V for SG3525A). Short-circuit current typ 80 mA; load capability up to 20 mA. Bypass with 0.1 µF to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-16 |
| Category | PMIC |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
SG3525AP013TRSG2525APSG3525AP013TRSG3525AP013TRSG2525ANSG3525AN
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VREF Output Voltage | VREF | 5 | 5.1 | 5.2 | V | Tj = 25 °C | 3 |
| Line Regulation | ∆VREF | 10 | 20 | mV | Vi = 8 to 35 V | 3 | |
| Load Regulation | ∆VREF | 20 | 50 | mV | IL = 0 to 20 mA | 3 | |
| Temp. Stability | ∆VREF/∆T | 20 | 50 | mV | Over Operating Range | 3 | |
| Total Output Variation (Line, Load and Temperature) | 4.95 | 5.25 | V | 3 | |||
| Short Circuit Current | 80 | 100 | mA | VREF = 0 Tj = 25 °C | 3 | ||
| Long Term Stability | ∆VREF | 20 | 50 | mV | Tj = 125 °C, 1000 hrs | 3 | |
| Initial Accuracy | -6 | 2 | 6 | % | Tj = 25 °C | 3 | |
| Voltage Stability | -2 | 1 | 2 | % | Vi = 8 to 35 V | 3 | |
| Temperature Stability | ∆f/∆T | -6 | 3 | 6 | % | Over Operating Range | 3 |
| Current Mirror | 1.7 | 2 | 2.2 | mA | IRT = 2 mA | 3 | |
| Clock Width | 0.3 | 0.5 | 1 | µs | Tj = 25 °C | 3 | |
| Sync Threshold | 1.2 | 2 | 2.8 | V | 3 | ||
| Sync Input Current | 1 | 2.5 | mA | Sync Voltage = 3.5 V | 3 | ||
| Input Offset Voltage | VOS | 2 | 10 | mV | 3 | ||
| Input Bias Current | Ib | 1 | 10 | µA | 3 | ||
| DC Open Loop Gain | Gv | 60 | 75 | dB | RL ≥ 10 MΩ | 3 | |
| Gain Bandwidth Product | 1 | 2 | MHz | Gv = 0 dB Tj = 25 °C | 3 | ||
| DC Transconductance | gM | 1.1 | 1.5 | ms | 30 KΩ ≤ RL ≤ 1 MΩ Tj = 25 °C | 3 | |
| Error Amplifier Output Low Level | 0.2 | 0.5 | V | 3 | |||
| Error Amplifier Output High Level | 3.8 | 5.6 | V | 3 | |||
| Common Mode Rejection | CMR | 60 | 75 | dB | VCM = 1.5 to 5.2 V | 3 | |
| Supply Voltage Rejection | PSR | 50 | 60 | dB | Vi = 8 to 35 V | 3 | |
| Maximum Duty-cycle | 45 | 49 | % | 4 | |||
| Input Threshold Zero Duty-cycle | 0.7 | 0.9 | V | 4 | |||
| Input Threshold Maximum Duty-cycle | 3.3 | 3.6 | V | 4 | |||
| Soft Start Current | 25 | 50 | 80 | µA | VSD = 0 V, VSS = 0 V | 4 | |
| Soft Start Low Level | 0.4 | 0.7 | V | VSD = 2.5 V | 4 | ||
| Shutdown Threshold | 0.6 | 0.8 | 1 | V | To outputs, VSS = 5.1 V Tj = 25 °C | 4 | |
| Shutdown Input Current | 0.4 | 1 | mA | VSD = 2.5 V | 4 | ||
| Output Low Level (each output) | 0.2 | 0.4 | V | Isink = 20 mA | 4 | ||
| Output Low Level (each output) | 1 | 2 | V | Isink = 100 mA | 4 | ||
| Output High Level (each output) | 18 | 19 | V | Isource = 20 mA | 4 | ||
| Output High Level (each output) | 17 | 18 | V | Isource = 100 mA | 4 | ||
| Under-Voltage Lockout | 6 | 7 | 8 | V | Vcomp and Vss = High | 4 | |
| IC Collector Leakage | 200 | µA | VC = 35 V | 4 | |||
| Rise Time | tr | 100 | 600 | ns | CL = 1 nF, Tj = 25 °C | 4 | |
| Fall Time | tf | 50 | 300 | ns | CL = 1 nF, Tj = 25 °C | 4 | |
| Supply Current | Is | 14 | 20 | mA | Vi = 35 V | 4 | |
| Input Voltage | Vi | 8 | 35 | V | 6 | ||
| Collector Supply Voltage | VC | 4.5 | 35 | V | 6 | ||
| Sink/Source Load Current (steady state) | 0 | 100 | mA | 6 | |||
| Sink/Source Load Current (peak) | 0 | 400 | mA | 6 | |||
| Reference Load Current | IR | 0 | 20 | mA | 6 | ||
| Oscillator Frequency Range | fOSC | 100 | 400 | Hz (min) / KHz (max) | 6 | ||
| Oscillator Timing Resistor | RT | 2 | 150 | KΩ | 6 | ||
| Oscillator Timing Capacitor | CT | 0.001 | 0.1 | µF | 6 | ||
| Dead Time Resistor Range | RD | 0 | 500 | Ω | 6 | ||
| Operating Ambient Temperature (SG3525A) | Top | 0 | 70 | °C | 2 | ||
| Supply Voltage | Vi | 40 | V | 2 | |||
| Collector Supply Voltage | VC | 40 | V | 2 | |||
| Oscillator Charging Current | IOSC | 5 | mA | 2 | |||
| Output Current, Source or Sink | Io | 500 | mA | 2 | |||
| Reference Output Current | IR | 50 | mA | 2 | |||
| Current through CT Terminal | IT | 5 | mA | 2 | |||
| Logic Inputs | -0.3 | 5.5 | V | 2 | |||
| Analog Inputs (printed upper limit: Vi) | -0.3 | V | 2 | ||||
| Total Power Dissipation | Ptot | 1000 | mW | Tamb = 70 °C | 2 | ||
| Junction Temperature Range | Tj | -55 | 150 | °C | 2 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 2 |
CAD (KiCad official)
- Symbol:
SG3525AP013TR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sg3525ap013tr-etched.step/sg3525ap013tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sg3525ap013tr.step/sg3525ap013tr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
sg3525ap013tr.step |
217 KB | You want the bare part, or you mark your own boards. |
sg3525ap013tr-etched.step |
3.4 MB | You want the part with SG3525AP013TR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 813 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (12 pp, sha256
249b8b0c18c356d5, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).