SG3525AN from STMicroelectronics, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INV_INPUT	input	Inverting input of the error amplifier. Common-mode range includes the 5.1 V reference so external divider resistors are typically not required.
2	NI_INPUT	input	Non-inverting input of the error amplifier. Typically tied to VREF (pin 16) via a divider for regulation feedback.
3	SYNC	bidirectional	Oscillator sync terminal. Allows multiple units to be slaved together, or a single unit synchronized to an external system clock. Sync threshold ~2 V, sync input current ~1 mA at 3.5 V.
4	OSC_OUTPUT	output	Oscillator clock output. Provides the internal clock waveform (typ. 3.5 V amplitude, 0.5 µs width) for external synchronization or diagnostics.
5	CT	passive	Oscillator timing capacitor terminal. Connect timing capacitor CT (0.001 µF to 0.1 µF) from this pin to ground to set the oscillator frequency (100 Hz-400 kHz).
6	RT	passive	Oscillator timing resistor terminal. Connect RT (2 kΩ to 150 kΩ) from this pin to ground. Together with CT and RD sets fosc ≈ 1 / (CT·(0.7·RT + 3·RD)).
7	DISCHARGE	passive	Discharge terminal. A resistor (0 to 500 Ω) placed between CT (pin 5) and DISCHARGE sets the dead-time (blanking) between outputs A and B.
8	SOFT_START	passive	Soft-start capacitor terminal. An external capacitor to ground is charged by an internal ~50 µA current source to gradually increase duty cycle at startup.
9	COMP	output	Error amplifier output / PWM comparator input. Compensation node; connect loop compensation network here. Output swing typ. 0.2-5.6 V.
10	SHUTDOWN	input	Pulse-by-pulse shutdown input. Controls both the soft-start circuit and the output stages; drives outputs off via the PWM latch. Threshold ~0.8 V (referenced to VSS=5.1 V), typ. 0.5 µs shutdown delay.
11	OUTPUT_A	output	PWM output A, totem-pole source/sink driver. Alternates with OUTPUT B at half the oscillator frequency. Source/sink capability >200 mA (peak 400 mA); LOW output in OFF state (NOR-logic output stage).
12	GROUND	power_in	Signal and power ground return for the device.
13	VC	power_in	Collector supply voltage for the output driver totem-poles. Range 4.5 V to 35 V (independent of VI); allows separate biasing of the output stage.
14	OUTPUT_B	output	PWM output B, totem-pole source/sink driver. Complementary to OUTPUT A (alternating pulses). Source/sink capability >200 mA (peak 400 mA); LOW in OFF state.
15	VI	power_in	Main input supply voltage (+VI). Operating range 8 V to 35 V. Undervoltage lockout keeps outputs off below ~7 V with ~500 mV hysteresis.
16	VREF	power_out	Internal 5.1 V precision reference output (trimmed to ±1 %). Short-circuit current ~80 mA; load current up to 20 mA. Bypass with 0.1 µF to ground.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	DIP-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

SG3525AN
SG3525ANSG2525AN
SG3525AP
SG3525ANSG2525AP

CAD (KiCad official)

Symbol: SG3525AN
Footprint: Package_DIP:DIP-16_W7.62mm
3D model: DIP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sg3525an.step`	505 KB	You want the bare part, or you mark your own boards.
`sg3525an-etched.step`	2.5 MB	You want the part with `SG3525AN` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 604 faces against 284 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (12 pp, sha256 e5422b04ca23d090, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF