RT9193-18GB
Public Made by Adomby adom
Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownRT9193-18GB
Richtek Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
RT9193-18GB from Richtek Tech, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input voltage. Operating range 2.5V to 5.5V (absolute max 6V). Requires a 1uF X7R input capacitor to GND for stability. |
| 2 | GND | power_in | Device ground reference. Common return for VIN, VOUT, EN and BP. |
| 3 | EN | input | Chip Enable, active high (TTL logic). VIH >= 1.2V enables the regulator; VIL <= 0.4V shuts it down. Input is high impedance (bias current ~0/100nA max), so a ~100kOhm pull-down to GND is recommended when the control signal is floating. Input range 0V to 5.5V. |
| 4 | BP | passive | Reference noise bypass pin. May be left floating; for lowest output noise (~100 uVrms, 10Hz-100kHz) connect a 22nF ceramic capacitor between BP and GND. |
| 5 | VOUT | power_out | Regulated output voltage, 1.8V nominal (-18 suffix), 300mA max load. Requires a 1uF X7R output capacitor to GND for stability. Current-limited (typ 400mA) and thermally protected (Tsd ~165 degC). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |
Ordering variants
Same part, different packaging or reel option.
RT9193-18GBBRT9193-18GBU5RT9193-18GBJ5RT9193-18GBQWRT9193-18GBF
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | ΔVOUT | -2 | 2 | % | IOUT = 1mA | 3 | |
| Current Limit | ILIM | 360 | 400 | mA | RLOAD = 1Ω | 3 | |
| Quiescent Current | IQ | 90 | 130 | μA | VEN ≥ 1.2V, IOUT = 0mA | 3 | |
| Dropout Voltage | VDROP | 170 | 200 | mV | IOUT = 200mA, VOUT > 2.8V | 3 | |
| Dropout Voltage | VDROP | 220 | 300 | mV | IOUT = 300mA, VOUT > 2.8V | 3 | |
| Line Regulation | ΔVLINE | 0.3 | % | VIN = (VOUT + 1V) to 5.5V, IOUT = 1mA | 3 | ||
| Load Regulation | ΔVLOAD | 0.6 | % | 1mA < IOUT < 300mA | 3 | ||
| Standby Current | ISTBY | 0.01 | 1 | μA | VEN = GND, Shutdown | 3 | |
| EN Input Bias Current | IIBSD | 0 | 100 | nA | VEN = GND or VIN | 4 | |
| EN Threshold Logic-Low Voltage | VIL | 0.4 | V | VIN = 3V to 5.5V, Shutdown | 4 | ||
| EN Threshold Logic-High Voltage | VIH | 1.2 | V | VIN = 3V to 5.5V, Start-Up | 4 | ||
| Supply Input Voltage | VIN | 6 | V | 3 | |||
| Power Dissipation, SOT-23-5 | PD | 400 | mW | TA = 25°C | 3 | ||
| Package Thermal Resistance, SOT-23-5 junction-to-ambient | θJA | 250 | °C/W | 3 | |||
| Package Thermal Resistance, SOT-23-5 junction-to-case | θJC | 25 | °C/W | 3 | |||
| Junction Temperature | TJ | 150 | °C | 3 | |||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10 sec. | 3 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 3 | |||
| ESD Susceptibility MM | 200 | V | Machine Model | 3 | |||
| Supply Input Voltage | VIN | 2.5 | 5.5 | V | 3 | ||
| EN Input Voltage | VEN | 0 | 5.5 | V | 3 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 3 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 3 |
CAD (KiCad official)
- Symbol:
RT9193-18GB - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
rt9193-18gb-etched.step/rt9193-18gb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt9193-18gb.step/rt9193-18gb.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
rt9193-18gb.step |
85 KB | You want the bare part, or you mark your own boards. |
rt9193-18gb-etched.step |
2.2 MB | You want the part with RT9193-18GB already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 538 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (14 pp, sha256
f6c77df0675f253b, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).