PJ71K30SC from PJSEMI, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground reference for the regulator. Connect to system ground; return path for input, output and quiescent current.
2	VOUT	power_out	Regulated output voltage pin. Fixed 3.0V nominal (±5%, 2.85V-3.15V) for PJ71K30SC at IOUT=10mA. Supplies up to 30mA typical (20mA min). Bypass to GND with a 10µF capacitor as shown in the Basic Circuits diagram.
3	VIN	power_in	Unregulated supply input. Absolute max 28V; recommended operating range 4V ≤ VIN ≤ 24V for the 3.0V variant. Bypass to GND with a 10µF capacitor. Voltage drop (VIN-VOUT) is typically 100mV at 1mA.

Key specifications

Parameter	Value
Manufacturer	PJSEMI
Package	SOT-23
Category	PMIC
Pins	3

Ordering variants

Same part, different packaging or reel option.

PJ71K30SC
PJ71K33SC
PJ71K36SC
PJ71K44SC
PJ71K50SC

CAD (KiCad official)

Symbol: PJ71K30SC
Footprint: Package_TO_SOT_SMD:SOT-23
3D model: SOT-23 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`pj71k30sc.step`	59 KB	You want the bare part, or you mark your own boards.
`pj71k30sc-etched.step`	1.6 MB	You want the part with `PJ71K30SC` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 400 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: PJSEMI datasheet (7 pp, sha256 a0676535e30f79a4, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF