component
NS8002
Public Made by Adomby adom
Shenzhen Nsiway Tech Audio Power OpAmps, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownNS8002
Shenzhen Nsiway Tech · Audio Power OpAmps · SOP-8
NS8002 from Shenzhen Nsiway Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SD | input | Shutdown control pin. Active-high shutdown: drive HIGH to disable the amplifier (low-power mode, typ. 1µA), drive LOW to enable normal operation. Must not be left floating. |
| 2 | Bypass | passive | Internal common-mode (VCC/2) bias bypass. Connect a 1.0µF capacitor from this pin to GND to filter the mid-rail reference and improve PSRR. |
| 3 | +IN | input | Non-inverting analog audio input to the internal op-amp. Typically AC-coupled through an input capacitor. |
| 4 | -IN | input | Inverting analog audio input to the internal op-amp. Used with an external feedback resistor (Rf) and input resistor (Ri) to set the closed-loop gain. |
| 5 | VO1 | output | Analog audio output 1 - one leg of the BTL bridge to the loudspeaker. Connect directly to one terminal of the 4Ω/8Ω load (no output coupling capacitor required). |
| 6 | VDD | power_in | Positive supply voltage input. Operating range 3.0V to 5.25V (abs-max 2.8-5.5V). Decouple with a 1.0µF tantalum (Cs) close to the pin. |
| 7 | GND | power_in | Power/ground return. Connect to the system ground plane. |
| 8 | VO2 | output | Analog audio output 2 - the second (inverted, Av=-1) leg of the BTL bridge to the loudspeaker. Connect directly to the other terminal of the 4Ω/8Ω load. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shenzhen Nsiway Tech |
| Package | SOP-8 |
| Category | Op-amp/Cmp |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 (Supply voltage) | VDD | 3 | 5.25 | V | 4 | ||
| 电源静态电流 (Quiescent supply current) | IDD | 6 | 10 | mA | VIN＝0V，Io=0A | 4 | |
| 关断漏电流 (Shutdown leakage current) | ISD | 1 | 20 | µA | 4 | ||
| 输出失调电压 (Output offset voltage) | VOS | 5.7 | 50 | mV | 4 | ||
| 输出电阻 (Output resistance) | RO | 7 | 8.5 | 10 | K | 4 | |
| 输出功率 (Output power) | PO | 1.8 | W | THD＝1%,f=1KHz, RL=4Ω | 4 | ||
| 输出功率 (Output power) | PO | 1.3 | W | THD＝1%,f=1KHz, RL=8Ω | 4 | ||
| 输出功率 (Output power) | PO | 1.7 | W | THD+N=10%,f=1KHz, RL=8Ω | 4 | ||
| 总谐波失真+噪声 (THD+N) | THD+N | 0.1 | % | AVD=2, 20Hz≤f≤20KHz, RL=4Ω, PO=1W | 4 | ||
| 电源抑制比 (Power supply rejection ratio) | PSRR | 65 | 80 | dB | 4 | ||
| 信噪比 (Signal-to-noise ratio) | SNR | 85 | dB | RL＝4Ω,Po＝1W | 4 | ||
| 高电平输入电压 (High-level input voltage, 5V supply) | VIH | 1.5 | V | 电源电压为 5V | 12 | ||
| 低电平输入电压 (Low-level input voltage, 5V supply) | VIL | 1.3 | V | 电源电压为 5V | 12 | ||
| 高电平输入电压 (High-level input voltage, 3V supply) | VIH | 1.3 | V | 电源电压为 3V | 12 | ||
| 低电平输入电压 (Low-level input voltage, 3V supply) | VIL | 1 | V | 电源电压为 3V | 12 | ||
| 电源电压范围 (Supply voltage range, absolute maximum) | VDD | 2.8 | 5.5 | V | 2 | ||
| 输入电压范围 (Input voltage range) | VIN | -0.3 | V | upper limit VDD | 2 | ||
| ESD 电压 HBM (ESD voltage, human body model) | 3000 | V | 2 | ||||
| ESD 电压 MM (ESD voltage, machine model) | 250 | V | 2 | ||||
| 工作温度范围 (Operating temperature range) | TA | -40 | 85 | ℃ | 2 | ||
| 存储温度范围 (Storage temperature range) | TSTG | -65 | 150 | ℃ | 2 | ||
| 最大结温 (Maximum junction temperature) | TJ | 150 | ℃ | 2 | |||
| 焊接温度 (Soldering temperature) | 220 | ℃ | 10s 内 | 2 | |||
| 结到外壳热阻 (Thermal resistance, junction to case) | θJC | 35 | oC/W | 2 | |||
| 结到环境热阻 (Thermal resistance, junction to ambient) | θJA | 140 | oC/W | 2 |
CAD (KiCad official)
- Symbol:
NS8002 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ns8002-etched.step/ns8002-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ns8002.step/ns8002.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
ns8002.step |
122 KB | You want the bare part, or you mark your own boards. |
ns8002-etched.step |
1.8 MB | You want the part with NS8002 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 437 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shenzhen Nsiway Tech datasheet (14 pp, sha256
abdf6c36ebb2278b, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).