component
MM74HCT08MTCX
Public Unreviewedby Ray
onsemi Logic Gates, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
PCB Footprint
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
Datasheet
Open in new tab ↗Loads on click. Unloads when scrolled away or the tab is hidden.
README
markdownMM74HCT08MTCX
onsemi · Logic Gates · TSSOP-14
MM74HCT08MTCX from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Gate 1 input A. TTL-compatible logic input (VIH >= 2.0V, VIL <= 0.8V) to the first 2-input AND gate; output Y1 = A1 AND B1. |
| 2 | B1 | input | Gate 1 input B. TTL-compatible logic input to the first 2-input AND gate; output Y1 = A1 AND B1. |
| 3 | Y1 | output | Gate 1 output. AND of A1 and B1. Drives up to 10 LS-TTL loads; guaranteed VOH >= VCC-0.1V at 20µA, VOL <= 0.4V at 4.0mA (VCC=4.5V). |
| 4 | A2 | input | Gate 2 input A. TTL-compatible logic input to the second 2-input AND gate; output Y2 = A2 AND B2. |
| 5 | B2 | input | Gate 2 input B. TTL-compatible logic input to the second 2-input AND gate; output Y2 = A2 AND B2. |
| 6 | Y2 | output | Gate 2 output. AND of A2 and B2. Drives up to 10 LS-TTL loads. |
| 7 | GND | power_in | Ground reference (0V). All input protection diodes return to this rail. |
| 8 | Y3 | output | Gate 3 output. AND of A3 and B3. Drives up to 10 LS-TTL loads. |
| 9 | A3 | input | Gate 3 input A. TTL-compatible logic input to the third 2-input AND gate; output Y3 = A3 AND B3. |
| 10 | B3 | input | Gate 3 input B. TTL-compatible logic input to the third 2-input AND gate; output Y3 = A3 AND B3. |
| 11 | Y4 | output | Gate 4 output. AND of A4 and B4. Drives up to 10 LS-TTL loads. |
| 12 | A4 | input | Gate 4 input A. TTL-compatible logic input to the fourth 2-input AND gate; output Y4 = A4 AND B4. |
| 13 | B4 | input | Gate 4 input B. TTL-compatible logic input to the fourth 2-input AND gate; output Y4 = A4 AND B4. |
| 14 | VCC | power_in | Positive supply voltage. Recommended operating range 4.5V to 5.5V; absolute max -0.5V to +7.0V. Decouple with a 100nF ceramic capacitor to GND close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
MM74HCT08MTCXMM74HCT08MTCXMMM74HCT08MTCXMXMM74HCT08MTCXSJMM74HCT08MTCXSJXMM74HCT08MTCXN
CAD (KiCad official)
- Symbol:
MM74HCT08MTCX - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (None pp, sha256
e913c83bee91e88e, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).