MCP7940NT-I from Microchip, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	X1	input	Quartz crystal input / external oscillator input. Connects to one terminal of the 32.768 kHz tuning-fork crystal (optimized for 6-9 pF load capacitance) with its external load capacitor to VSS. Also usable as the external clock input when driving the device from an external oscillator.
2	X2	output	Quartz crystal output. Connects to the second terminal of the 32.768 kHz crystal with its external load capacitor to VSS. Leave floating when using an external oscillator driving X1.
3	VBAT	power_in	Battery backup supply input, 1.3 V to 5.5 V. Maintains RTCC and SRAM when VCC is lost; typical timekeeping backup current is 925 nA at 3.0 V. Tie to VSS if the battery backup feature is not used.
4	VSS	power_in	Device ground (0 V) reference for VCC and VBAT rails and all logic signals.
5	SDA	bidirectional	Bidirectional I2C serial data (open-drain). Requires an external pull-up resistor to VCC (typ. 10 kΩ at 100 kHz or 2 kΩ at 400 kHz). Data may change only while SCL is low; changes while SCL is high signal Start/Stop conditions.
6	SCL	input	I2C serial clock input from the bus master, used to synchronize data transfer to/from the device. Supports clock rates up to 400 kHz. Schmitt-trigger input with 50 ns spike suppression; requires an external pull-up to VCC.
7	MFP	output	Multifunction output (open-drain). Configurable as alarm output on an alarm match, as a selectable-frequency square-wave output, or as a general-purpose output driven by the OUT bit in the CONTROL register. Requires an external pull-up resistor to VCC (typ. 10 kΩ); leave floating if unused. VOL = 0.40 V at IOL = 3.0 mA (VCC = 4.5 V).
8	VCC	power_in	Primary power supply, 1.8 V to 5.5 V. Typical timekeeping current 1.2 uA at 3.3 V; SRAM/RTCC register operating current is 300 uA (read) / 400 uA (write) at VCC = 5.5 V, SCL = 400 kHz. Power-fail switchover to VBAT occurs at VTRIP (1.3-1.7 V).
EP	EP	passive	Exposed thermal/mechanical pad on the underside of the TDFN package. May be connected to VSS or left floating (per the Note under Table 3-1). Connection to VSS is recommended for mechanical anchoring and improved thermal performance.

Key specifications

Parameter	Value
Manufacturer	Microchip
Package	SOIC-8
Category	RTC
Pins	9

Ordering variants

Same part, different packaging or reel option.

MCP7940NT-IMNY
MCP7940NT-I/MNY
MCP7940NT-ISN
MCP7940NT-IMS
MCP7940NT-IST
MCP7940NT-IP

CAD (KiCad official)

Symbol: MCP7940NT-I
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip datasheet (56 pp, sha256 4aafe310fbafe313, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF