A dual 12-bit digital-to-analog converter with an SPI interface, in SOIC-14, for generating two independent analog voltages from a microcontroller. Each channel (VOUTA, VOUTB) has its own external reference input and an output buffer that drives loads directly, with optional 1x or 2x gain. A shared LDAC pin lets both outputs update at the same instant after loading, which matters for coordinated waveforms, and a shutdown pin parks unused channels. Twelve bits give 4096 steps per channel. Runs 2.7-5.5 V.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Positive supply voltage input, 2.7V to 5.5V, referenced to VSS. Bypass with 0.1 µF ceramic (and optional 10 µF tantalum) to VSS for good DAC performance.
2	NC	unconnected	No internal connection. Leave floating or tie to ground per layout preference.
3	CS	input	SPI chip-select input, active low. Must be driven low to enable the serial clock (SCK) and serial data (SDI) inputs and to shift a 16-bit write command into the device.
4	SCK	input	SPI-compatible serial clock input. Supports clock rates up to 20 MHz; SDI is latched on the rising edge of SCK while CS is low.
5	SDI	input	SPI-compatible serial data input. Receives the 16-bit configuration/DAC word (channel select, buffered/gain/shutdown bits + 12-bit data) MSB first.
6	NC	unconnected	No internal connection.
7	NC	unconnected	No internal connection.
8	LDAC	input	Latch DAC synchronization input, active low. Transfers the input latch registers of both channels to their DAC output registers (VOUTA and VOUTB update simultaneously) when driven low. May be tied to VSS to update on the rising edge of CS.
9	SHDN	input	Hardware shutdown input, active low. When low, both DAC channels are shut down and the output amplifiers are disconnected (outputs present a known ~500 kΩ typical load to ground).
10	VOUTB	output	DAC channel B analog voltage output from the dedicated rail-to-rail output op-amp. Output range VSS to VDD; short-circuit current ≈ 15 mA typ, slew rate ≈ 0.55 V/µs.
11	VREFB	input	Voltage reference input for DAC channel B. Sets the reference for channel B's string DAC; input range VSS to VDD. Input impedance ≈ 165 kΩ (unbuffered mode); may be tied to VDD.
12	VSS	power_in	Analog ground / current return path for the device. Connect to the board ground plane through a low-impedance connection; tie to analog ground if a split plane exists.
13	VREFA	input	Voltage reference input for DAC channel A. Sets the reference for channel A's string DAC; input range VSS to VDD. Input impedance ≈ 165 kΩ (unbuffered mode); may be tied to VDD.
14	VOUTA	output	DAC channel A analog voltage output from the dedicated rail-to-rail output op-amp. Output range VSS to VDD; short-circuit current ≈ 15 mA typ, slew rate ≈ 0.55 V/µs.

Key specifications

Parameter	Value
Type	Dual DAC
Resolution	12-bit per channel
Channels	2 (VOUTA, VOUTB)
Interface	SPI (up to 20 MHz)
Reference	external per channel (VREFA/VREFB)
Output	buffered, 1x/2x gain
Sync update	LDAC pin
Supply voltage	2.7-5.5 V
Package	SOIC-14

Ordering variants

Same part, different packaging or reel option.

MCP4922-E/SL (SOIC-14)
MCP4922-E/P (PDIP-14)

CAD (KiCad official)

Symbol: Analog_DAC:MCP4922
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Technology datasheet (48 pp, sha256 8c507a2bce321888, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF