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MCP3204 12-Bit SPI ADC

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by Ray

12-bit 4-channel successive-approximation ADC with an SPI interface.

adcsar12-bitspimultichannelmicrochipsoic-14
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README

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MCP3204

Microchip · Analog-to-Digital Converter · SOIC-14

The MCP3204 is a 12-bit successive-approximation ADC with four input channels (single-ended or two differential pairs) and an SPI interface. It samples at up to 100 ksps, using an external reference, and is a simple, popular way to add multiple analog inputs to an MCU. The MCP3208 is the 8-channel version.

Pinout

Pin Name Type Function
1 CH0 input Analog input channel 0. Usable as a single-ended input (0 V to VREF) or as the IN+ of the CH0/CH1 pseudo-differential pair.
2 CH1 input Analog input channel 1. Usable as a single-ended input (0 V to VREF) or as the IN- of the CH0/CH1 pseudo-differential pair (IN- limited to ±100 mV from VSS).
3 CH2 input Analog input channel 2. Usable as a single-ended input (0 V to VREF) or as the IN+ of the CH2/CH3 pseudo-differential pair.
4 CH3 input Analog input channel 3. Usable as a single-ended input (0 V to VREF) or as the IN- of the CH2/CH3 pseudo-differential pair (IN- limited to ±100 mV from VSS).
5 NC unconnected No connection. Leave floating or tie to ground; do not use as a signal via.
6 NC unconnected No connection. Leave floating or tie to ground; do not use as a signal via.
7 DGND power_in Digital ground return for internal digital circuitry. Tie to the system ground plane; keep separate trace back to AGND star point where possible.
8 CS/SHDN input Active-low chip select / shutdown. Falling edge starts a conversion cycle; must be pulled high between conversions to end conversion and place the device in low-power standby (typ. 500 nA IDDS).
9 DIN input SPI serial data input (MOSI). Clocks in the start bit, SGL/DIFF bit, and channel select bits on the rising edge of CLK. SPI modes 0,0 and 1,1 supported.
10 DOUT tri_state SPI serial data output (MISO). Shifts out the 12-bit conversion result MSB first on the falling edge of CLK. High-impedance when CS is high.
11 CLK input SPI serial clock. Initiates conversion on the start bit and clocks out each result bit. fCLK max 2.0 MHz at VDD=5V, 1.0 MHz at VDD=2.7V; minimum clock rate limited by sample-cap droop (see Section 6.2).
12 AGND power_in Analog ground return for internal analog circuitry. Tie to a quiet analog ground plane; join to DGND at a single star point.
13 VREF power_in Reference voltage input. Sets the analog input full-scale range (VREF = full-scale). Valid range 0.25 V to VDD; IREF typ. 100 µA (max 150 µA). Bypass close to the pin.
14 VDD power_in Positive supply, +2.7 V to +5.5 V. IDD typ. 320 µA (max 400 µA) with DOUT unloaded. Decouple with 0.1 µF close to the pin.

Key specifications

Parameter Value
Resolution 12-bit
Architecture SAR (successive approximation)
Channels 4 single-ended / 2 differential
Sample rate Up to 100 ksps
Interface SPI
Reference External
Supply voltage 2.7 V to 5.5 V
Operating temperature -40 C to 85 C

Ordering variants

Same part, different packaging or reel option.

  • MCP3204I/P
  • MCP3204-BI/P
  • MCP3204-CI/P
  • MCP3204I/SL
  • MCP3204-BI/SL
  • MCP3204-CI/SL
  • MCP3204I/ST
  • MCP3204-BI/ST
  • MCP3204-CI/ST

CAD (KiCad official)

  • Symbol: mcp3204.kicad_sym
  • Footprint: mcp3204.kicad_mod
  • 3D model: SOIC-14 body from KiCad Package_SO/SOIC-14_3.9x8.7mm_P1.27mm.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip datasheet (40 pp, sha256 89bc1e17c35e2bb1, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF