The MCP23S17 is a 16-bit general-purpose I/O expander controlled over SPI. Its two 8-bit ports have configurable direction, pull-ups, polarity, and interrupt-on-change, and three hardware address pins let up to eight devices share one SPI bus. It is the SPI counterpart of the I2C MCP23017.

Pinout

Pin	Name	Type	Function
1	GPB0	bidirectional	PORTB bit 0 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up. Max sink/source 25 mA per pin.
2	GPB1	bidirectional	PORTB bit 1 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
3	GPB2	bidirectional	PORTB bit 2 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
4	GPB3	bidirectional	PORTB bit 3 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
5	GPB4	bidirectional	PORTB bit 4 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
6	GPB5	bidirectional	PORTB bit 5 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
7	GPB6	bidirectional	PORTB bit 6 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
8	GPB7	bidirectional	PORTB bit 7 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
9	VDD	power_in	Positive supply. Operating range 1.8 V to 5.5 V (-40 to +85 C), 2.7 V to 5.5 V (-40 to +85 C), or 4.5 V to 5.5 V (-40 to +125 C). Decouple to VSS with a local bypass capacitor.
10	VSS	power_in	Ground reference. Return for all device currents; connect to system ground plane.
11	CS	input	SPI chip select input (active-low). Frames each SPI transaction; must be driven low to enable serial communication with this device.
12	SCK	input	SPI serial clock input. Maximum 10 MHz. Clocks data into SI on the master-configured edge and out on SO.
13	SI	input	SPI serial data input (MOSI). Receives command, address and write-data bytes from the SPI master.
14	SO	output	SPI serial data output (MISO). Drives read-data back to the SPI master; high-impedance while CS is high.
15	A0	input	Hardware address bit 0. Sets the least-significant bit of the 3-bit chip address matched during SPI transactions. Must be externally biased (tied to VDD or VSS); do not leave floating.
16	A1	input	Hardware address bit 1. Must be externally biased (tied to VDD or VSS).
17	A2	input	Hardware address bit 2. Must be externally biased (tied to VDD or VSS). Combined with A0/A1 allows up to eight MCP23S17 devices to share one SPI bus.
18	RESET	input	Active-low hardware reset input. Forces all registers to their POR defaults while asserted. Must be externally biased (tie to VDD through a pull-up if unused); do not leave floating.
19	INTB	output	Interrupt output for PORTB. Polarity and drive configurable as active-high, active-low, or open-drain via IOCON.INTPOL/ODR. Can be OR'd with INTA when IOCON.MIRROR = 1.
20	INTA	output	Interrupt output for PORTA. Polarity and drive configurable as active-high, active-low, or open-drain via IOCON.INTPOL/ODR. Can be OR'd with INTB when IOCON.MIRROR = 1.
21	GPA0	bidirectional	PORTA bit 0 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
22	GPA1	bidirectional	PORTA bit 1 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
23	GPA2	bidirectional	PORTA bit 2 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
24	GPA3	bidirectional	PORTA bit 3 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
25	GPA4	bidirectional	PORTA bit 4 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
26	GPA5	bidirectional	PORTA bit 5 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
27	GPA6	bidirectional	PORTA bit 6 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.
28	GPA7	bidirectional	PORTA bit 7 bidirectional I/O. Can be enabled for interrupt-on-change and/or internal weak pull-up. Defaults to input at power-up.

Key specifications

Parameter	Value
Type	16-bit I/O expander
Interface	SPI (up to 10 MHz)
I/O	16, two 8-bit ports (GPA/GPB)
Per-pin features	Direction, pull-up, polarity, interrupt-on-change
Addressing	3 hardware address pins (up to 8 on a bus)
Supply voltage	1.8 V to 5.5 V
Operating temperature	-40 C to 85 C

Ordering variants

Same part, different packaging or reel option.

MCP23S17SP
MCP23S17E/SP
MCP23S17SO
MCP23S17E/SO
MCP23S17T-E/SO
MCP23S17SS
MCP23S17E/SS
MCP23S17T-E/SS
MCP23S17ML
MCP23S17E/ML
MCP23S17T-E/ML

CAD (KiCad official)

Symbol: mcp23s17.kicad_sym
Footprint: mcp23s17.kicad_mod
3D model: SOIC-28 wide body from KiCad Package_SO/SOIC-28W_7.5x17.9mm_P1.27mm.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip datasheet (42 pp, sha256 14159c6f5655e943, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MCP23S17 SPI GPIO Expander

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README

MCP23S17

Pinout

Key specifications

Ordering variants

CAD (KiCad official)

Provenance