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Contents

README

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MB85RS64TPNF-G-JNERE2

FUJITSU · FRAM · SOP-8

MB85RS64TPNF-G-JNERE2 from FUJITSU, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select input; L level activates device and H level deactivates device with SO going High-Z.
2 SO tri_state Serial Data Output pin that outputs FRAM array and status register read data with High-Z during standby.
3 WP input Write Protect input pin that controls status register write protection based on WEL and WPEN bits.
4 VSS power_in Ground (0 V) supply pin.
5 SI input Serial Data Input pin for receiving op-code, address, and write data.
6 SCK input Serial Clock input pin that synchronizes SI input on rising edges and SO output on falling edges.
7 HOLD input Hold input pin that suspends serial operation and drives SO to High-Z when held at L level without deselecting device.
8 VDD power_in Supply Voltage input pin.

Key specifications

Parameter Value
Manufacturer FUJITSU
Package SOP-8
Category Memory
Pins 8

CAD (KiCad official)

  • Symbol: MB85RS64TPNF-G-JNERE2
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: mb85rs64tpnf-g-jnere2-etched.step / mb85rs64tpnf-g-jnere2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mb85rs64tpnf-g-jnere2.step / mb85rs64tpnf-g-jnere2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FUJITSU datasheet (34 pp, sha256 4ca8dcb15e8b4747, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF