component
LP3992-33B5F
Public Made by Adomby adom
LOWPOWER Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP3992-33B5F
LOWPOWER · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LP3992-33B5F from LOWPOWER, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input voltage. Recommended operating range 2.5V to 5.5V (absolute max 6.5V). Requires a >=1µF input capacitor placed within 0.5 inch of the pin. |
| 2 | GND | power_in | Device ground return. Return input and output capacitors to a clean analog ground. |
| 3 | EN | input | Chip enable (active high, TTL logic). VIH >= 1.4V enables the regulator; VIL <= 0.4V places the device in shutdown (<0.01µA typical). May be tied to VIN for always-on operation. Absolute max EN voltage is VIN+0.3V. |
| 4 | NC | unconnected | No internal connection. May be left floating. |
| 5 | VOUT | power_out | Regulated 3.3V output (±3% accuracy at 1mA). Delivers up to 300mA with 220mV typical dropout at 300mA. Requires a >=1µF ceramic output capacitor (ESR >25mΩ acceptable) placed within 0.5 inch of the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LOWPOWER |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |
Ordering variants
Same part, different packaging or reel option.
LP3992-33B5FLP3992-33B5FJ5FLP3992-33B5FB3F
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | ΔVOUT | -3 | 3 | % | IOUT = 1mA | 4 | |
| Output Loading Current | ILOAD | 300 | mA | VEN=VIN, VIN>2.5V | 4 | ||
| Current Limit | ILIM | 420 | 450 | mA | RLOAD = 1Ω | 4 | |
| Quiescent Current | IQ | 75 | 130 | μA | VEN ≥ 1.2V, IOUT = 0mA | 4 | |
| Dropout Voltage | VDROP | 130 | 200 | mV | IOUT = 200mA, VOUT > 2.8V | 4 | |
| Dropout Voltage | VDROP | 220 | 300 | mV | IOUT = 300mA, VOUT > 2.8V | 4 | |
| Line Regulation | ΔVLINE | 0.2 | %/V | VIN = (VOUT + 1V) to 5.5V, IOUT = 50mA | 4 | ||
| Load Regulation | ΔLOAD | 2 | %/A | 1mA < IOUT < 300mA | 4 | ||
| Standby Current | ISTBY | 0.01 | 1 | μA | VEN = GND, Shutdown | 4 | |
| EN Input Bias Current | IIBSD | 1.5 | 3.5 | μA | VEN = 3V | 4 | |
| EN Logic-Low Voltage | VIL | 0.4 | V | VIN = 3V to 5.5V, Shutdown | 4 | ||
| EN Logic-High Voltage | VIH | 1.4 | V | VIN = 3V to 5.5V, Start-Up | 4 | ||
| Output Noise Voltage | 300 | uVRMS | 10Hz to 100kHz, IOUT = 200mA, COUT = 1µF | 4 | |||
| Supply Input Voltage (absolute maximum) | 6.5 | V | 3 | ||||
| Other Pin Voltage | -0.3 | V | Relative to VIN+0.3V upper limit as printed | 3 | |||
| Power Dissipation | PD | 500 | mW | TA = 25°C, T/SOT23-5 | 3 | ||
| Maximum Junction Temperature | 150 | °C | 3 | ||||
| Maximum Soldering Temperature | 260 | °C | at leads, 10 sec | 3 | |||
| Storage Temperature Range | -65 | 165 | °C | 3 | |||
| ESD HBM | 2 | kV | Human Body Model | 3 | |||
| ESD MM | 200 | V | Machine Model | 3 | |||
| Supply Input Voltage (recommended) | 2.5 | 5.5 | V | 3 | |||
| EN Input Voltage | 0 | V | 3 | ||||
| Operation Junction Temperature Range | -40 | 125 | °C | 3 | |||
| Operation Ambient Temperature Range | -40 | 85 | °C | 3 | |||
| Power Supply Rejection Rate | -76 | dB | f = 1kHz COUT = 1µF, IOUT = 100mA | 4 | |||
| Power Supply Rejection Rate | -65 | dB | f = 10kHz | 4 | |||
| Thermal Shutdown Temperature | TSD | 150 | °C | 4 | |||
| Thermal Resistance Junction-to-Ambient | (JA) | 195 | °C/W | SOT23-5/SOT23 package | 3 | ||
| Thermal Resistance Junction-to-Case | (JC) | 60 | °C/W | SOT23-5/SOT23 package | 3 |
CAD (KiCad official)
- Symbol:
LP3992-33B5F - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lp3992-33b5f-etched.step/lp3992-33b5f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp3992-33b5f.step/lp3992-33b5f.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
lp3992-33b5f.step |
85 KB | You want the bare part, or you mark your own boards. |
lp3992-33b5f-etched.step |
2.6 MB | You want the part with LP3992-33B5F already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 610 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LOWPOWER datasheet (9 pp, sha256
c4874862660fdd11, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).