Steps a wide 3.8 to 36 V input down to a regulated rail at up to 3 A, with both power MOSFETs integrated so the external parts are an inductor and a few capacitors. A resistor divider at FB sets the output, EN gives a precision enable threshold, and the power-good flag (PG) signals when the rail is in regulation. The device runs a fixed switching frequency (order-code option, 400 kHz to 2.1 MHz) and drops to power-save mode at light load. The PowerPAD carries heat into the board.

Pinout

Pin	Name	Type	Function
1	PGND	power_in	Power ground terminal. Connect to system ground and AGND. Connect to input bypass capacitor with short wide traces to minimize switching-loop inductance.
2	VIN	power_in	Input supply to regulator (3.8 V to 36 V operating, 38 V abs max). Connect a high-quality bypass capacitor (or capacitors) directly between this pin and PGND.
3	EN	input	Enable input to regulator (analog precision-enable). High = ON, low = OFF. Can be tied directly to VIN. Do not float. Voltage must not exceed VIN by more than 0.3 V.
4	PG	output	Open-drain power-good flag output (0 V to 22 V abs max). Connect to a suitable voltage supply through a current-limiting pull-up resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Leave open if unused.
5	FB	input	Feedback input to the regulator's error amplifier. Connect to the tap point of the external feedback voltage divider that sets VOUT (1 V to 24 V adjustable). Do not float. Do not ground.
6	VCC	power_out	Internal 5-V LDO output that supplies internal control circuits. Connect a high-quality 1-µF ceramic capacitor from this pin to GND. Do not connect to external loads (may be used as logic supply for the power-good flag pull-up). Abs max 5.5 V.
7	BOOT	passive	Bootstrap supply for the internal high-side MOSFET gate driver. Connect a high-quality 100-nF ceramic capacitor between BOOT and SW. Abs max BOOT-to-SW = 5.5 V.
8	SW	power_out	Regulator switch node - connection of the internal high-side and low-side power MOSFETs. Connect to the external power inductor. Handles the full switched inductor current; keep this trace short and away from sensitive nodes. SW abs max −0.3 V to VIN+0.3 V (steady) / −3.5 V to 38 V for <100-ns transients.
PAD	AGND	power_in	Analog ground for regulator and system, and the thermal pad. Ground reference for internal references and logic - all electrical parameters are measured with respect to this pin. On the HSOIC package the pad on the bottom of the device serves as both the AGND connection and the thermal connection to the heat-sink ground plane; must be soldered to a ground plane for correct electrical and thermal performance.

Key specifications

Parameter	Value
Type	Synchronous buck (step-down) converter
Input	3.8-36 V
Output current	3 A
Switching freq	400 kHz / 1.4 MHz / 2.1 MHz (by part)
Integrated FETs	Yes (high + low side)
Features	Precision EN, power-good, power-save mode
Package	HSOIC-8 (PowerPAD)

Ordering variants

Same part, different packaging or reel option.

LMR33630ADDAR (HSOIC-8, 400 kHz)
LMR33630BDDAR (HSOIC-8, 1.4 MHz)
LMR33630CDDAR (HSOIC-8, 2.1 MHz)

CAD (KiCad official)

Symbol: Regulator_Switching:LMR33630ADDA (KiCad official)
Footprint: Package_SO:Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm_ThermalVias
3D model: HSOIC-8 PowerPAD (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (60 pp, sha256 3b0920a4e56a0b3f, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF