L6599ATDTR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Css	input	Soft-start pin. External capacitor to GND plus resistor to RFmin sets the maximum oscillator frequency and the time constant for the frequency-shift soft-start ramp. Internally discharged on shutdown or when ISEN exceeds 0.8 V.
2	DELAY	input	Delayed shutdown on overcurrent. RC network to GND sets max duration of an overcurrent condition before switching stops (charged by internal 150 uA source when ISEN>0.8V). Above 2 V forces Css discharge; above 3.5 V stops switching; restarts as pin drops below 0.3 V.
3	CF	passive	Oscillator timing capacitor. Capacitor to GND is charged/discharged by internal current generators programmed by the RFmin network, setting the converter switching frequency.
4	RFmin	output	Minimum oscillator frequency setting. Provides a precise 2 V reference; resistor from this pin to GND defines the current setting the minimum switching frequency. Optocoupler phototransistor connected here modulates frequency for feedback control.
5	STBY	input	Burst-mode threshold. Compared to internal 1.24 V reference; below the reference IC enters idle (burst) mode with reduced quiescent current, restarts when pin exceeds 1.29 V. Tie to RFmin if burst mode is not used.
6	ISEN	input	Current sense input for primary current (sense resistor or capacitive divider). Above 0.8 V threshold (50 mV hysteresis) Css is internally discharged (frequency-shift OCP). Above 1.5 V latches the device off. Tie to GND if unused.
7	LINE	input	Line sensing input for AC or DC (post-PFC) brownout protection via resistor divider from HV bus. Below 1.24 V shuts down (not latched) IC; 13 uA current hysteresis source. Internal Zener clamp; Zener conduction also shuts IC down. Bias between 1.24 and 6 V if unused.
8	DIS	input	Latched device shutdown. When voltage exceeds 1.85 V the IC is latched off; latch clears only when Vcc drops below UVLO. Useful for OTP/OVP implementation. Tie to GND if unused.
9	PFC_STOP	output	Open-drain ON/OFF control of the PFC controller. Pulled low when the IC is shut down (DIS>1.85V, ISEN>1.5V, LINE>6V, STBY<1.24V) or when DELAY>2V; releases when DELAY falls below 0.3 V. Open during UVLO. Leave unconnected if unused.
10	GND	power_in	Chip ground. Current return for both the low-side gate-drive current and IC bias current. Keep bias-component ground track separate from pulsed switching currents.
11	LVG	output	Low-side gate-drive output for the lower MOSFET of the half-bridge. Capable of 0.3 A min. source / 0.7 A min. sink peak current. Actively pulled to GND during UVLO.
12	Vcc	power_in	Supply voltage for the IC signal section and the low-side gate driver. Operating range 8.85 to 16 V, VccOn ~10.7 V, VccOff ~8.15 V; internal clamp at ~17 V. A small 0.1 uF bypass to GND is recommended.
13	N.C.	unconnected	No connection. High-voltage spacer pin left unconnected internally to increase creepage distance between the low-voltage side and the high-voltage floating pins (14-16).
14	OUT	power_in	High-side gate-drive floating ground (half-bridge midpoint). Current return for the high-side gate driver; connect carefully to avoid large negative spikes. Max slew rate 50 V/ns; up to 600 V floating operation.
15	HVG	output	High-side floating gate-drive output for the upper MOSFET of the half-bridge. 0.3 A min. source / 0.7 A min. sink peak drive; internal resistor to OUT keeps pin non-floating during UVLO.
16	VBOOT	power_in	High-side gate-drive floating supply (bootstrap rail). Bootstrap capacitor between VBOOT and OUT is refreshed via an internal synchronous bootstrap DMOS driven in-phase with LVG. Rated up to 618 V absolute maximum with respect to GND.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SO-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

L6599ATDTR

CAD (KiCad official)

Symbol: L6599ATDTR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SO-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`l6599atdtr.step`	217 KB	You want the bare part, or you mark your own boards.
`l6599atdtr-etched.step`	2.4 MB	You want the part with `L6599ATDTR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 605 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (32 pp, sha256 1e1f355db14cc0ab, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF