L6599ADTR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Css	passive	Soft-start pin. External capacitor to GND plus a resistor to RFmin (pin 4) sets the maximum oscillator frequency and the frequency-shift time constant during startup. Internally discharged whenever the chip turns off (Vcc<UVLO, LINE<1.24 V or >6 V, DIS>1.85 V, ISEN>1.5 V, DELAY>2 V) or when ISEN exceeds 0.8 V while it stays above 0.75 V.
2	DELAY	passive	Delayed-shutdown-upon-overcurrent pin. Capacitor and resistor to GND set the maximum OCP duration and the auto-restart delay. Charged by a 150 uA internal current source each time ISEN exceeds 0.8 V; at 2 V Css is fully discharged (max frequency), at 3.5 V the IC stops switching, and it soft-restarts when the pin falls below 0.3 V.
3	CF	passive	Timing capacitor. External capacitor from this pin to GND is charged and discharged by internal current generators programmed by the network on RFmin (pin 4), setting the converter switching frequency. Typical VCFpeak = 3.9 V, VCFvalley = 0.9 V.
4	RFmin	passive	Minimum-oscillator-frequency-setting pin. Provides a precise 2 V reference; a resistor from this pin to GND sets the minimum operating (open-loop) frequency. The feedback optocoupler phototransistor connects to this pin through a resistor to set the maximum frequency, and an R-C series network sets soft-start frequency shift. Max source current 2 mA.
5	STBY	input	Burst-mode operation threshold input. Voltage related to feedback control is compared to an internal 1.24 V reference; below the reference the IC enters idle state, above (reference + 50 mV) it resumes switching (soft-start not invoked). Tie to RFmin (pin 4) if burst mode is not used.
6	ISEN	input	Current sense input for OCP. Senses primary current through a sense resistor or capacitive divider (filtered for average). Above 0.8 V (50 mV hysteresis) Css is discharged and frequency shifts up limiting throughput; a second comparator at 1.5 V latches the device off. Latch cleared by cycling Vcc below UVLO. Tie to GND if unused.
7	LINE	input	Line-sensing input for AC/DC brownout protection. Connected via resistor divider to the HV bus; below 1.24 V shuts down (not latched) and discharges Css, above 1.24 V re-enables operation (soft-started). 13 uA internal hysteresis current on while V<1.24 V. Internal Zener clamps the pin (activation causes non-latched shutdown). Bias between 1.24-6 V if unused.
8	DIS	input	Latched device shutdown input. When the pin voltage exceeds 1.85 V the IC latches off and drops to a 'before-startup' consumption level. The latch is cleared only when Vcc is cycled below UVLO. Tie to GND if the function is not used.
9	PFC_STOP	output	Open-drain ON/OFF control for an external PFC controller. Normally open; pulled low (drives PFC off) when the IC is shut down by DIS>1.85 V, ISEN>1.5 V, LINE>6 V, STBY<1.24 V, or when DELAY>2 V. Open during UVLO. Leave unconnected if not used. Vmax = Vcc.
10	GND	power_in	Chip ground. Current return for both the low-side gate driver and the IC bias current. All bias-component ground returns should connect here on a dedicated track kept separate from any pulsed-current return path.
11	LVG	output	Low-side gate-drive output for the lower MOSFET of the half-bridge leg. Capable of 0.3 A source / 0.8 A sink peak drive current. Actively pulled to GND during UVLO. Absolute max -0.3 to Vcc+0.3 V.
12	Vcc	power_in	Supply voltage for the signal section and the low-side gate driver. Operating range 8.85-16 V (UVLO turn-on ~10.7 V, turn-off ~8.15 V). Internally clamped at ~17 V. A 0.1 uF decoupling cap to GND is recommended for a clean signal bias.
13	N.C.	unconnected	High-voltage spacer, not internally connected. Provided to isolate the high-voltage pins from Vcc and ease creepage-distance compliance with safety regulations on the PCB.
14	OUT	power_in	High-side gate-drive floating ground / half-bridge midpoint return. Return path for the high-side gate-drive current; connects to the source of the high-side MOSFET (bridge switching node). Layout carefully to avoid large negative spikes. Slew rate up to 50 V/ns supported.
15	HVG	output	High-side floating gate-drive output for the upper MOSFET of the half-bridge. Capable of 0.3 A source / 0.8 A sink peak drive current. An internal resistor to OUT (pin 14) prevents the pin from floating during UVLO. ESD immunity guaranteed up to 900 V.
16	VBOOT	power_in	High-side floating gate-drive supply. Bootstrap capacitor connects between this pin and OUT (pin 14) and is fed by an internal synchronous bootstrap DMOS driven in-phase with the low-side gate drive (replaces the usual external fast-recovery diode). Floating supply rating -1 to 618 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SO-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

L6599ADTR
L6599AN

CAD (KiCad official)

Symbol: L6599ADTR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SO-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`l6599adtr.step`	217 KB	You want the bare part, or you mark your own boards.
`l6599adtr-etched.step`	2.4 MB	You want the part with `L6599ADTR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 586 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (35 pp, sha256 65a4e3d0af4b421e, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF