ISO3086DWR from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC1	power_in	Logic-side supply. 3.15-3.6 V for 3.3-V operation or 4.5-5.5 V for 5-V operation. Decouple with local bypass capacitors to GND1.
2	GND1	power_in	Logic-side ground return for VCC1. Pins 2, 7, and 8 are internally tied and must all be connected to the logic-side ground plane.
3	R	output	Receiver output (logic side). CMOS output driven by the isolated receiver comparator sensing bus pins A/B. Output current ±8 mA.
4	RE	input	Active-low receiver enable. Drive low (or leave open) to enable the receiver output R; drive high to place R in high-impedance. VIH ≥ 2 V, VIL ≤ 0.8 V.
5	DE	input	Driver enable. Drive high to enable the differential driver outputs Y/Z; drive low or leave open to place them in high-impedance. VIH ≥ 2 V, VIL ≤ 0.8 V.
6	D	input	Driver data input (logic side). CMOS-level input; state at D controls the differential state driven onto Y/Z when DE is asserted.
7	GND1	power_in	Logic-side ground return for VCC1. Internally common with pins 2 and 8.
8	GND1	power_in	Logic-side ground return for VCC1. Internally common with pins 2 and 7.
9	GND2	power_in	Bus-side ground return for VCC2. Internally common with pins 10 and 15; isolated from GND1 by the 2500-Vrms isolation barrier.
10	GND2	power_in	Bus-side ground return for VCC2. Internally common with pins 9 and 15.
11	Y	output	Driver noninverting output on the bus side (RS-485 full-duplex TX+). Drives differential pair Y/Z with up to ±60 mA and withstands −7 V to +12 V common-mode.
12	Z	output	Driver inverting output on the bus side (RS-485 full-duplex TX−). Complementary to Y; three-stated when DE is low.
13	B	input	Receiver inverting input on the bus side (RS-485 full-duplex RX−). Differential input range VID −12 V to +12 V, common-mode range −7 V to +12 V.
14	A	input	Receiver noninverting input on the bus side (RS-485 full-duplex RX+). Paired with B; fail-safe biased for bus open/short/idle.
15	GND2	power_in	Bus-side ground return for VCC2. Internally common with pins 9 and 10.
16	VCC2	power_in	Bus-side supply. 4.5-5.5 V for 5-V operation. Decouple with local bypass capacitors to GND2.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16-300mil
Category	Interface
Pins	16

Ordering variants

Same part, different packaging or reel option.

ISO3086DWR

CAD (KiCad official)

Symbol: ISO3086DWR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16-300mil (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`iso3086dwr.step`	217 KB	You want the bare part, or you mark your own boards.
`iso3086dwr-etched.step`	2.9 MB	You want the part with `ISO3086DWR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 707 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (33 pp, sha256 f568a60935325c4d, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF