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HEF4518BT

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Nexperia Counters, Dividers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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HEF4518BT

Nexperia · Counters, Dividers · SOIC-16

HEF4518BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP0 input Counter 1 clock input, LOW-to-HIGH triggered; counter advances when 1CP0 transitions LOW-to-HIGH and 1CP1 is HIGH.
2 1CP1 input Counter 1 clock input, HIGH-to-LOW triggered; counter advances when 1CP1 transitions HIGH-to-LOW and 1CP0 is LOW.
3 1Q0 output Counter 1 buffered output from bit 0 of the 4-bit BCD counter; resets to LOW when 1MR is HIGH.
4 1Q1 output Counter 1 buffered output from bit 1 of the 4-bit BCD counter; resets to LOW when 1MR is HIGH.
5 1Q2 output Counter 1 buffered output from bit 2 of the 4-bit BCD counter; resets to LOW when 1MR is HIGH.
6 1Q3 output Counter 1 buffered output from bit 3 of the 4-bit BCD counter; resets to LOW when 1MR is HIGH.
7 1MR input Asynchronous master reset input for counter 1; HIGH level resets all counter outputs (1Q0 to 1Q3) to LOW independent of clock inputs.
8 VSS power_in Ground supply voltage (0 V reference).
9 2CP0 input Counter 2 clock input, LOW-to-HIGH triggered; counter advances when 2CP0 transitions LOW-to-HIGH and 2CP1 is HIGH.
10 2CP1 input Counter 2 clock input, HIGH-to-LOW triggered; counter advances when 2CP1 transitions HIGH-to-LOW and 2CP0 is LOW.
11 2Q0 output Counter 2 buffered output from bit 0 of the 4-bit BCD counter; resets to LOW when 2MR is HIGH.
12 2Q1 output Counter 2 buffered output from bit 1 of the 4-bit BCD counter; resets to LOW when 2MR is HIGH.
13 2Q2 output Counter 2 buffered output from bit 2 of the 4-bit BCD counter; resets to LOW when 2MR is HIGH.
14 2Q3 output Counter 2 buffered output from bit 3 of the 4-bit BCD counter; resets to LOW when 2MR is HIGH.
15 2MR input Asynchronous master reset input for counter 2; HIGH level resets all counter outputs (2Q0 to 2Q3) to LOW independent of clock inputs.
16 VDD power_in Positive supply voltage input; operating range 3.0 V to 15.0 V with CMOS low power dissipation.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: HEF4518BT
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: hef4518bt-etched.step / hef4518bt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef4518bt.step / hef4518bt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 e8c61850ae16899b, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF