HEF4094BTTJ from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	STR	input	Strobe input. When STR is HIGH, data in the 8-stage shift register is transferred to the 8-bit storage register (latched to the parallel outputs).
2	D	input	Serial data input. Sampled on the LOW-to-HIGH transition of CP and shifted into stage 0 of the shift register.
3	CP	input	Shift register clock input. Data on D is shifted on the LOW-to-HIGH (positive) transition of CP.
4	QP0	tri_state	3-state parallel output bit 0 from the storage register. High-impedance when OE is LOW; drives CMOS output levels when OE is HIGH.
5	QP1	tri_state	3-state parallel output bit 1 from the storage register. High-impedance when OE is LOW.
6	QP2	tri_state	3-state parallel output bit 2 from the storage register. High-impedance when OE is LOW.
7	QP3	tri_state	3-state parallel output bit 3 from the storage register. High-impedance when OE is LOW.
8	VSS	power_in	Ground supply voltage (0 V reference). All limiting values and logic levels are referenced to VSS.
9	QS1	output	Serial output that mirrors stage 7 data on the LOW-to-HIGH transition of CP; used to cascade devices when clock edges are fast.
10	QS2	output	Serial output that mirrors stage 7 data on the HIGH-to-LOW transition of CP; used to cascade devices when clock edges are slow.
11	QP7	tri_state	3-state parallel output bit 7 from the storage register. High-impedance when OE is LOW.
12	QP6	tri_state	3-state parallel output bit 6 from the storage register. High-impedance when OE is LOW.
13	QP5	tri_state	3-state parallel output bit 5 from the storage register. High-impedance when OE is LOW.
14	QP4	tri_state	3-state parallel output bit 4 from the storage register. High-impedance when OE is LOW.
15	OE	input	Active-HIGH output enable. When HIGH the QP0-QP7 outputs are driven; when LOW they are placed into a high-impedance OFF-state. Does not affect the internal register contents.
16	VDD	power_in	Positive supply voltage. Recommended operating range 3 V to 15 V (absolute maximum 18 V).

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	TSSOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

HEF4094BTTJ

CAD (KiCad official)

Symbol: HEF4094BTTJ
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`hef4094bttj.step`	205 KB	You want the bare part, or you mark your own boards.
`hef4094bttj-etched.step`	2.3 MB	You want the part with `HEF4094BTTJ` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 597 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (15 pp, sha256 0020655a9e8cad90, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF