HEF4094BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	STR	input	Strobe input. When HIGH, data in the 8-bit shift register is transferred into the 8-bit storage register that drives the QP0-QP7 parallel outputs.
2	D	input	Serial data input. Sampled on the LOW-to-HIGH transition of CP and shifted into the first stage of the shift register.
3	CP	input	Clock input for the 8-stage shift register. Data on D is shifted on the LOW-to-HIGH (positive) transition of CP.
4	QP0	tri_state	Parallel output bit 0 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
5	QP1	tri_state	Parallel output bit 1 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
6	QP2	tri_state	Parallel output bit 2 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
7	QP3	tri_state	Parallel output bit 3 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
8	VSS	power_in	Ground supply voltage (0 V reference). All input/output voltages are referenced to VSS.
9	QS1	output	Serial output for cascading. Data appears at QS1 on the LOW-to-HIGH transition of CP (allows cascading when clock edges are fast).
10	QS2	output	Serial output for cascading. Data appears at QS2 on the next HIGH-to-LOW transition of CP (allows cascading when clock edges are slow).
11	QP7	tri_state	Parallel output bit 7 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
12	QP6	tri_state	Parallel output bit 6 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
13	QP5	tri_state	Parallel output bit 5 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
14	QP4	tri_state	Parallel output bit 4 from the storage register. 3-state: driven when OE is HIGH, high-impedance when OE is LOW.
15	OE	input	Output enable input. HIGH enables the QP0-QP7 parallel outputs; LOW places them in a high-impedance OFF-state. Does not affect the state of the shift or storage registers.
16	VDD	power_in	Positive supply voltage. Recommended operating range 3 V to 15 V; absolute max 18 V referenced to VSS.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

HEF4094BTT
HEF4094BTTT

CAD (KiCad official)

Symbol: HEF4094BT
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`hef4094bt.step`	217 KB	You want the bare part, or you mark your own boards.
`hef4094bt-etched.step`	2.1 MB	You want the part with `HEF4094BT` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 559 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (15 pp, sha256 0020655a9e8cad90, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF