component
HEF4093BT
Public Unreviewedby Ray
Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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markdownHEF4093BT
Nexperia · Gates · SOIC-14
HEF4093BT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1, Schmitt trigger input A. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 2 | 1B | input | Gate 1, Schmitt trigger input B. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 3 | 1Y | output | Gate 1 NAND output. Push-pull CMOS output; Y = NOT(A AND B). |
| 4 | 2Y | output | Gate 2 NAND output. Push-pull CMOS output; Y = NOT(A AND B). |
| 5 | 2A | input | Gate 2, Schmitt trigger input A. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 6 | 2B | input | Gate 2, Schmitt trigger input B. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 7 | VSS | power_in | Ground reference, 0 V. Negative supply rail for the device. |
| 8 | 3A | input | Gate 3, Schmitt trigger input A. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 9 | 3B | input | Gate 3, Schmitt trigger input B. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 10 | 3Y | output | Gate 3 NAND output. Push-pull CMOS output; Y = NOT(A AND B). |
| 11 | 4Y | output | Gate 4 NAND output. Push-pull CMOS output; Y = NOT(A AND B). |
| 12 | 4A | input | Gate 4, Schmitt trigger input A. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 13 | 4B | input | Gate 4, Schmitt trigger input B. CMOS logic input with hysteresis; unused inputs must be tied to VDD, VSS, or another input. |
| 14 | VDD | power_in | Positive supply voltage. Recommended operating range 3 V to 15 V; absolute max 18 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
HEF4093BTT
CAD (KiCad official)
- Symbol:
HEF4093BT - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (14 pp, sha256
f160789ec027b791, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).