HEF4081BT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Gate 1 input A. CMOS logic input; VIH ≥ 3.5 V @ VDD=5 V, VIL ≤ 1.5 V @ VDD=5 V. Input leakage ±0.1 µA typ. Unused inputs must be tied to VDD or VSS.
2	1B	input	Gate 1 input B. CMOS logic input; same electrical characteristics as 1A. Unused inputs must be tied to VDD or VSS.
3	1Y	output	Gate 1 output; 1Y = 1A AND 1B. Fully buffered CMOS output, VOH ≥ 4.95 V and VOL ≤ 0.05 V @ VDD=5 V with
4	2Y	output	Gate 2 output; 2Y = 2A AND 2B. Fully buffered CMOS output with standardized symmetrical drive.
5	2A	input	Gate 2 input A. CMOS logic input; unused inputs must be tied to VDD or VSS.
6	2B	input	Gate 2 input B. CMOS logic input; unused inputs must be tied to VDD or VSS.
7	VSS	power_in	Ground reference (0 V). All voltages in the datasheet are referenced to VSS.
8	3A	input	Gate 3 input A. CMOS logic input; unused inputs must be tied to VDD or VSS.
9	3B	input	Gate 3 input B. CMOS logic input; unused inputs must be tied to VDD or VSS.
10	3Y	output	Gate 3 output; 3Y = 3A AND 3B. Fully buffered CMOS output.
11	4Y	output	Gate 4 output; 4Y = 4A AND 4B. Fully buffered CMOS output.
12	4A	input	Gate 4 input A. CMOS logic input; unused inputs must be tied to VDD or VSS.
13	4B	input	Gate 4 input B. CMOS logic input; unused inputs must be tied to VDD or VSS.
14	VDD	power_in	Positive supply voltage. Recommended operating range 3 V to 15 V; absolute max 18 V. Typical supply current IDD ≤ 1 µA @ VDD=15 V for static inputs.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

HEF4081BTT

CAD (KiCad official)

Symbol: HEF4081BT
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`hef4081bt.step`	195 KB	You want the bare part, or you mark your own boards.
`hef4081bt-etched.step`	2.1 MB	You want the part with `HEF4081BT` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 541 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (11 pp, sha256 98a345e3e99a74a2, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF