HEF4069UBT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Inverter 1 input. CMOS logic input with internal clamp diodes to VSS and VDD; input voltage range 0 V to VDD, with clamping currents limited to ±10 mA. Input capacitance approximately 7.5 pF.
2	1Y	output	Inverter 1 output. CMOS push-pull output; drives complementary logic level of 1A. VOH ≥ VDD-0.05 V and VOL ≤ 0.05 V at
3	2A	input	Inverter 2 input. CMOS logic input with input clamp diodes to VSS and VDD; input leakage typ ±0.1 µA at VDD = 15 V.
4	2Y	output	Inverter 2 output. CMOS push-pull output; complementary logic level of 2A.
5	3A	input	Inverter 3 input. CMOS logic input with internal clamp diodes; input voltage range 0 V to VDD.
6	3Y	output	Inverter 3 output. CMOS push-pull output; complementary logic level of 3A.
7	VSS	power_in	Ground reference (0 V). Common return for logic and supply currents.
8	4Y	output	Inverter 4 output. CMOS push-pull output; complementary logic level of 4A.
9	4A	input	Inverter 4 input. CMOS logic input with clamp diodes to VSS and VDD.
10	5Y	output	Inverter 5 output. CMOS push-pull output; complementary logic level of 5A.
11	5A	input	Inverter 5 input. CMOS logic input with clamp diodes to VSS and VDD.
12	6Y	output	Inverter 6 output. CMOS push-pull output; complementary logic level of 6A.
13	6A	input	Inverter 6 input. CMOS logic input with clamp diodes to VSS and VDD.
14	VDD	power_in	Positive supply voltage. Recommended operating range 3.0 V to 15.0 V (absolute max 18 V); supply current typ 0.25 µA to 1.0 µA static, 50 mA absolute max. Decouple to VSS with a local ceramic capacitor.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

HEF4069UBTT
HEF4069UBTTT

CAD (KiCad official)

Symbol: HEF4069UBT
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`hef4069ubt.step`	195 KB	You want the bare part, or you mark your own boards.
`hef4069ubt-etched.step`	2.4 MB	You want the part with `HEF4069UBT` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 602 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (13 pp, sha256 479940d50b7b564a, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF