HEF4053BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	2Y1	bidirectional	Switch 2 independent input/output Y1. Analog signal path to/from 2Z when S2 = HIGH and E = LOW. Signal range VEE to VDD.
2	2Y0	bidirectional	Switch 2 independent input/output Y0. Analog signal path to/from 2Z when S2 = LOW and E = LOW. Signal range VEE to VDD.
3	3Y1	bidirectional	Switch 3 independent input/output Y1. Analog signal path to/from 3Z when S3 = HIGH and E = LOW. Signal range VEE to VDD.
4	3Z	bidirectional	Switch 3 common input/output Z. Analog common terminal of the third SPDT switch. Signal range VEE to VDD.
5	3Y0	bidirectional	Switch 3 independent input/output Y0. Analog signal path to/from 3Z when S3 = LOW and E = LOW. Signal range VEE to VDD.
6	E	input	Enable input, active LOW. When E = LOW the selected channel in each switch is ON; when E = HIGH all switches are OFF. Digital logic level referenced to VSS (VDD).
7	VEE	power_in	Negative analog supply voltage. Sets the lower end of the analog signal range. May be tied to VSS for single-supply operation, or driven below VSS (down to -18 V vs VDD) for split-supply level shifting.
8	VSS	power_in	Ground / digital supply return. Reference (0 V) for the digital logic (Sn, E) and typically for the lower analog rail.
9	S3	input	Digital select input for switch 3. LOW routes 3Y0 to 3Z; HIGH routes 3Y1 to 3Z (with E = LOW).
10	S2	input	Digital select input for switch 2. LOW routes 2Y0 to 2Z; HIGH routes 2Y1 to 2Z (with E = LOW).
11	S1	input	Digital select input for switch 1. LOW routes 1Y0 to 1Z; HIGH routes 1Y1 to 1Z (with E = LOW).
12	1Y0	bidirectional	Switch 1 independent input/output Y0. Analog signal path to/from 1Z when S1 = LOW and E = LOW. Signal range VEE to VDD.
13	1Y1	bidirectional	Switch 1 independent input/output Y1. Analog signal path to/from 1Z when S1 = HIGH and E = LOW. Signal range VEE to VDD.
14	1Z	bidirectional	Switch 1 common input/output Z. Analog common terminal of the first SPDT switch. Signal range VEE to VDD.
15	2Z	bidirectional	Switch 2 common input/output Z. Analog common terminal of the second SPDT switch. Signal range VEE to VDD.
16	VDD	power_in	Positive supply voltage. Recommended operating range 3 V to 15 V referenced to VSS; absolute maximum 18 V. Also sets the upper end of the analog signal range and the digital logic HIGH level.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-16
Category	Interface
Pins	16

Ordering variants

Same part, different packaging or reel option.

HEF4053BTT
HEF4053BTTT

CAD (KiCad official)

Symbol: HEF4053BT
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`hef4053bt.step`	217 KB	You want the bare part, or you mark your own boards.
`hef4053bt-etched.step`	2.3 MB	You want the part with `HEF4053BT` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 581 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (16 pp, sha256 b87534e2e0345fdb, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF