HEF4013BT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1Q	output	True output of flip-flop 1. CMOS push-pull output; VOH ≥ 4.95 V at VDD=5 V, IOH up to -1.7 mA at VO=2.5 V.
2	1Q_N	output	Complement (inverted) output of flip-flop 1. CMOS push-pull output; VOH ≥ 4.95 V at VDD=5 V.
3	1CP	input	Clock input of flip-flop 1. LOW-to-HIGH edge-triggered with Schmitt-trigger action for slow rise/fall times. Max clock frequency 7 MHz (typ 14 MHz) at VDD=5 V.
4	1CD	input	Asynchronous clear-direct (reset) input of flip-flop 1. Active HIGH; forces 1Q LOW and 1Q_N HIGH regardless of clock.
5	1D	input	Data input of flip-flop 1. Sampled on the LOW-to-HIGH transition of 1CP; set-up time 40 ns (min) at VDD=5 V.
6	1SD	input	Asynchronous set-direct (preset) input of flip-flop 1. Active HIGH; forces 1Q HIGH and 1Q_N LOW regardless of clock.
7	VSS	power_in	Ground reference, 0 V.
8	2SD	input	Asynchronous set-direct (preset) input of flip-flop 2. Active HIGH; forces 2Q HIGH and 2Q_N LOW regardless of clock.
9	2D	input	Data input of flip-flop 2. Sampled on the LOW-to-HIGH transition of 2CP.
10	2CD	input	Asynchronous clear-direct (reset) input of flip-flop 2. Active HIGH; forces 2Q LOW and 2Q_N HIGH regardless of clock.
11	2CP	input	Clock input of flip-flop 2. LOW-to-HIGH edge-triggered with Schmitt-trigger action for slow rise/fall times.
12	2Q_N	output	Complement (inverted) output of flip-flop 2. CMOS push-pull output.
13	2Q	output	True output of flip-flop 2. CMOS push-pull output.
14	VDD	power_in	Positive supply voltage. Recommended operating range 3 V to 15 V; absolute maximum 18 V.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	SOIC-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

HEF4013BT
HEF4013BTT

CAD (KiCad official)

Symbol: HEF4013BT
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`hef4013bt.step`	195 KB	You want the bare part, or you mark your own boards.
`hef4013bt-etched.step`	2.1 MB	You want the part with `HEF4013BT` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 533 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (14 pp, sha256 de5f450f49d3bded, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF