GL850G-HHY22 from Genesys Logic, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDD	power_in	3.3 V analog power input for internal analog circuits (USB PHY, PLL).
2	DM2	bidirectional	USB 2.0 downstream port 2, D- differential data line.
3	DP2	bidirectional	USB 2.0 downstream port 2, D+ differential data line.
4	RREF	passive	USB PHY bias reference. Connect a 680 Ω resistor from RREF to AGND to set the USB transmitter bias current.
5	AVDD	power_in	3.3 V analog power input for internal analog circuits.
6	X1	input	12 MHz crystal input, or external 12/27/48 MHz clock input (only 12 MHz supported on SSOP-28; SEL48/SEL27 select pins are not brought out).
7	X2	output	12 MHz crystal output. Leave open if driving X1 from an external oscillator.
8	DM3	bidirectional	USB 2.0 downstream port 3, D- differential data line.
9	DP3	bidirectional	USB 2.0 downstream port 3, D+ differential data line.
10	AVDD	power_in	3.3 V analog power input for internal analog circuits.
11	DM4	bidirectional	USB 2.0 downstream port 4, D- differential data line.
12	DP4	bidirectional	USB 2.0 downstream port 4, D+ differential data line.
13	RESET#	input	Active-low external reset input, 5 V tolerant. Internally pulled high through ~10 kΩ. Drive low to reset the whole chip.
14	TEST/SCL	bidirectional	Dual-function pin. TEST: 0 = normal operation (internal pull-down), 1 = test mode. In SSOP-28/QFN-28 it also serves as the I2C clock output for an external 24C02 EEPROM.
15	GND	power_in	Common ground return.
16	DVDD	power_in	3.3 V digital power input for the digital core.
17	PSELF	input	Self/bus power strap, 5 V tolerant. 0 = bus-powered hub, 1 = self-powered hub.
18	PGANG	bidirectional	Gang/Individual power-management strap and status output. Default input at power-on reset; sampled during strapping (gang input = 1, individual input = 0), then switches to an output that is high in normal mode and low when the hub is suspended. SSOP-28 supports GANG mode only.
19	OVCUR2#	input	Active-low over-current indicator for downstream ports 3-4 in GANG mode, 5 V tolerant. Flag asserts when OVCUR is low for more than 3 ms.
20	PWREN2#	output	Active-low power-enable output for downstream ports 3-4 in GANG mode. *Power switch is not supported in the GL850G-22 version - this output is non-functional on GL850G-HHY22.
21	OVCUR1#	input	Active-low over-current indicator for downstream ports 1-2 in GANG mode, 5 V tolerant. In GANG mode OVCUR1# is the only over-current flag used.
22	PWREN1#	output	Active-low power-enable output for downstream ports 1-2 in GANG mode. In GANG mode PWREN1# is the only power-enable output used. *Power switch not supported in GL850G-22 version.
23	V5	power_in	5 V power input to the on-chip 5 V→3.3 V regulator. Leave NC when using an external 3.3 V regulator.
24	V33	power_out	5 V→3.3 V regulator output AND 3.3 V supply pin (SSOP-28/QFN-28). Bypass to ground; also drives AVDD/DVDD externally.
25	DM0	bidirectional	USB 2.0 upstream (USPORT) port, D- differential data line.
26	DP0	bidirectional	USB 2.0 upstream (USPORT) port, D+ differential data line.
27	DM1	bidirectional	USB 2.0 downstream port 1, D- differential data line.
28	DP1	bidirectional	USB 2.0 downstream port 1, D+ differential data line.

Key specifications

Parameter	Value
Manufacturer	Genesys Logic
Package	SSOP-28-208mil
Category	Interface
Pins	28

Ordering variants

Same part, different packaging or reel option.

GL850G-HHY22HHYXX
GL850G-HHY22MNYXX
GL850G-HHY22OHYXX

CAD (KiCad official)

Symbol: GL850G-HHY22
Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
3D model: SSOP-28-208mil (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`gl850g-hhy22.step`	362 KB	You want the bare part, or you mark your own boards.
`gl850g-hhy22-etched.step`	3.4 MB	You want the part with `GL850G-HHY22` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 847 faces against 447 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Genesys Logic datasheet (39 pp, sha256 58ba9f67e305425f, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF