component
GD32F303RET6
Public Unreviewedby Ray
GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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markdownGD32F303RET6
GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
GD32F303RET6 from GigaDevice Semicon Beijing, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup battery supply for RTC and backup registers when VDD is absent (1.8-3.6 V). |
| 2 | PC13/TAMPER-RTC | bidirectional | GPIO Port C bit 13. Alternate: TAMPER-RTC (RTC tamper detection / RTC alarm out). Powered from VBAT domain - limited drive. |
| 3 | PC14/OSC32IN | bidirectional | GPIO Port C bit 14. Alternate: OSC32IN low-speed (32.768 kHz) crystal input. Powered from VBAT domain. |
| 4 | PC15/OSC32OUT | bidirectional | GPIO Port C bit 15. Alternate: OSC32OUT low-speed (32.768 kHz) crystal output. Powered from VBAT domain. |
| 5 | OSCIN | input | High-speed external (HSE) crystal / clock input. Can be remapped to PD0 (PD0/PD1 cannot be used for EXTI in this package). |
| 6 | OSCOUT | output | High-speed external (HSE) crystal output. Can be remapped to PD1. |
| 7 | NRST | bidirectional | Active-low bidirectional device reset. Internal weak pull-up; drive low externally to reset. Also driven low by internal reset sources. |
| 8 | PC0 | bidirectional | GPIO Port C bit 0. Alternate: ADC012_IN10 (ADC0/1/2 channel 10 analog input). |
| 9 | PC1 | bidirectional | GPIO Port C bit 1. Alternate: ADC012_IN11. |
| 10 | PC2 | bidirectional | GPIO Port C bit 2. Alternate: ADC012_IN12. |
| 11 | PC3 | bidirectional | GPIO Port C bit 3. Alternate: ADC012_IN13. |
| 12 | VSSA | power_in | Analog ground reference for ADC, DAC and reset circuitry. Connect to solid analog-ground plane. |
| 13 | VDDA | power_in | Analog supply (2.6-3.6 V) for ADC, DAC, reset and internal analog blocks. Decouple with 100 nF + 1 uF close to pin. |
| 14 | PA0-WKUP | bidirectional | GPIO Port A bit 0. Alternates: WKUP (standby wake), USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI. |
| 15 | PA1 | bidirectional | GPIO Port A bit 1. Alternates: USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1. |
| 16 | PA2 | bidirectional | GPIO Port A bit 2. Alternates: USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, SPI0_IO2. |
| 17 | PA3 | bidirectional | GPIO Port A bit 3. Alternates: USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, SPI0_IO3. |
| 18 | VSS_4 | power_in | Digital ground return #4. Tie all VSS_x pins together to the ground plane. |
| 19 | VDD_4 | power_in | Digital core/IO supply #4 (2.6-3.6 V). Decouple with 100 nF near pin. |
| 20 | PA4 | bidirectional | GPIO Port A bit 4. Alternates: SPI0_NSS, USART1_CK, ADC01_IN4, DAC0_OUT0. Remap: SPI2_NSS, I2S2_WS. |
| 21 | PA5 | bidirectional | GPIO Port A bit 5. Alternates: SPI0_SCK, ADC01_IN5, DAC0_OUT1. |
| 22 | PA6 | bidirectional | GPIO Port A bit 6. Alternates: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN, TIMER12_CH0. Remap: TIMER0_BRKIN. |
| 23 | PA7 | bidirectional | GPIO Port A bit 7. Alternates: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON, TIMER13_CH0. Remap: TIMER0_CH0_ON. |
| 24 | PC4 | bidirectional | GPIO Port C bit 4. Alternate: ADC01_IN14. |
| 25 | PC5 | bidirectional | GPIO Port C bit 5. Alternate: ADC01_IN15. |
| 26 | PB0 | bidirectional | GPIO Port B bit 0. Alternates: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON. Remap: TIMER0_CH1_ON. |
| 27 | PB1 | bidirectional | GPIO Port B bit 1. Alternates: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON. Remap: TIMER0_CH2_ON. |
| 28 | PB2/BOOT1 | bidirectional | GPIO Port B bit 2, also BOOT1 boot-select strap (sampled with BOOT0 at reset). 5 V tolerant. |
| 29 | PB10 | bidirectional | GPIO Port B bit 10 (5 V tolerant). Alternates: I2C1_SCL, USART2_TX. Remap: TIMER1_CH2. |
| 30 | PB11 | bidirectional | GPIO Port B bit 11 (5 V tolerant). Alternates: I2C1_SDA, USART2_RX. Remap: TIMER1_CH3. |
| 31 | VSS_1 | power_in | Digital ground return #1. |
| 32 | VDD_1 | power_in | Digital core/IO supply #1 (2.6-3.6 V). Decouple with 100 nF near pin. |
| 33 | PB12 | bidirectional | GPIO Port B bit 12 (5 V tolerant). Alternates: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS. |
| 34 | PB13 | bidirectional | GPIO Port B bit 13 (5 V tolerant). Alternates: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK. |
| 35 | PB14 | bidirectional | GPIO Port B bit 14 (5 V tolerant). Alternates: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0. |
| 36 | PB15 | bidirectional | GPIO Port B bit 15 (5 V tolerant). Alternates: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1. |
| 37 | PC6 | bidirectional | GPIO Port C bit 6 (5 V tolerant). Alternates: I2S1_MCK, TIMER7_CH0, SDIO_D6. Remap: TIMER2_CH0. |
| 38 | PC7 | bidirectional | GPIO Port C bit 7 (5 V tolerant). Alternates: I2S2_MCK, TIMER7_CH1, SDIO_D7. Remap: TIMER2_CH1. |
| 39 | PC8 | bidirectional | GPIO Port C bit 8 (5 V tolerant). Alternates: TIMER7_CH2, SDIO_D0. Remap: TIMER2_CH2. |
| 40 | PC9 | bidirectional | GPIO Port C bit 9 (5 V tolerant). Alternates: TIMER7_CH3, SDIO_D1. Remap: TIMER2_CH3. |
| 41 | PA8 | bidirectional | GPIO Port A bit 8 (5 V tolerant). Alternates: USART0_CK, TIMER0_CH0, CK_OUT0 (MCO), CTC_SYNC. |
| 42 | PA9 | bidirectional | GPIO Port A bit 9 (5 V tolerant). Alternates: USART0_TX, TIMER0_CH1. |
| 43 | PA10 | bidirectional | GPIO Port A bit 10 (5 V tolerant). Alternates: USART0_RX, TIMER0_CH2. |
| 44 | PA11 | bidirectional | GPIO Port A bit 11 (5 V tolerant). Alternates: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3. |
| 45 | PA12 | bidirectional | GPIO Port A bit 12 (5 V tolerant). Alternates: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP. |
| 46 | PA13/JTMS/SWDIO | bidirectional | Default JTAG TMS / SWD IO after reset. Can be remapped to PA13 GPIO once debug is disabled. 5 V tolerant. |
| 47 | VSS_2 | power_in | Digital ground return #2. |
| 48 | VDD_2 | power_in | Digital core/IO supply #2 (2.6-3.6 V). Decouple with 100 nF near pin. |
| 49 | PA14/JTCK/SWCLK | bidirectional | Default JTAG TCK / SWD CLK after reset. Can be remapped to PA14 GPIO once debug is disabled. 5 V tolerant. |
| 50 | PA15/JTDI | bidirectional | Default JTAG TDI. Alternates: SPI2_NSS, I2S2_WS. Remap: TIMER1_CH0, TIMER1_ETI, PA15 GPIO, SPI0_NSS. 5 V tolerant. |
| 51 | PC10 | bidirectional | GPIO Port C bit 10 (5 V tolerant). Alternates: UART3_TX, SDIO_D2. Remap: USART2_TX, SPI2_SCK, I2S2_CK. |
| 52 | PC11 | bidirectional | GPIO Port C bit 11 (5 V tolerant). Alternates: UART3_RX, SDIO_D3. Remap: USART2_RX, SPI2_MISO. |
| 53 | PC12 | bidirectional | GPIO Port C bit 12 (5 V tolerant). Alternates: UART4_TX, SDIO_CK. Remap: USART2_CK, SPI2_MOSI, I2S2_SD. |
| 54 | PD2 | bidirectional | GPIO Port D bit 2 (5 V tolerant). Alternates: TIMER2_ETI, SDIO_CMD, UART4_RX. |
| 55 | PB3/JTDO | bidirectional | Default JTAG TDO. Alternates: SPI2_SCK, I2S2_CK. Remap: PB3 GPIO, TRACESWO, TIMER1_CH1, SPI0_SCK. 5 V tolerant. |
| 56 | PB4/NJTRST | bidirectional | Default JTAG NJTRST (active-low). Alternate: SPI2_MISO. Remap: TIMER2_CH0, PB4 GPIO, SPI0_MISO. 5 V tolerant. |
| 57 | PB5 | bidirectional | GPIO Port B bit 5. Alternates: I2C0_SMBA, SPI2_MOSI, I2S2_SD. Remap: TIMER2_CH1, SPI0_MOSI. |
| 58 | PB6 | bidirectional | GPIO Port B bit 6 (5 V tolerant). Alternates: I2C0_SCL, TIMER3_CH0. Remap: USART0_TX, SPI0_IO2. |
| 59 | PB7 | bidirectional | GPIO Port B bit 7 (5 V tolerant). Alternates: I2C0_SDA, TIMER3_CH1. Remap: USART0_RX, SPI0_IO3. |
| 60 | BOOT0 | input | Boot mode select strap sampled at reset (together with BOOT1). Selects main Flash / system memory / embedded SRAM boot. |
| 61 | PB8 | bidirectional | GPIO Port B bit 8 (5 V tolerant). Alternates: TIMER3_CH2, SDIO_D4, TIMER9_CH0. Remap: I2C0_SCL, CAN0_RX. |
| 62 | PB9 | bidirectional | GPIO Port B bit 9 (5 V tolerant). Alternates: TIMER3_CH3, SDIO_D5, TIMER10_CH0. Remap: I2C0_SDA, CAN0_TX. |
| 63 | VSS_3 | power_in | Digital ground return #3. |
| 64 | VDD_3 | power_in | Digital core/IO supply #3 (2.6-3.6 V). Decouple with 100 nF near pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-64(10x10) |
| Category | MCU |
| Pins | 64 |
Ordering variants
Same part, different packaging or reel option.
GD32F303RET6RCT6GD32F303RET6RCT7GD32F303RET6GD32F303RET6RET7GD32F303RET6RGT6GD32F303RET6RIT6GD32F303RET6RKT6GD32F303RET6CCT6GD32F303RET6CET6GD32F303RET6CGT6GD32F303RET6CCU6GD32F303RET6CEU6GD32F303RET6CGU6GD32F303RET6VCT6GD32F303RET6VET6GD32F303RET6VET7GD32F303RET6VGT6GD32F303RET6VGT7GD32F303RET6VIT6GD32F303RET6VKT6GD32F303RET6ZCT6GD32F303RET6ZET6GD32F303RET6ZGT6GD32F303RET6ZIT6GD32F303RET6ZKT6
CAD (KiCad official)
- Symbol:
GD32F303RET6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice Semicon Beijing datasheet (103 pp, sha256
df6b797095a9416e, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).