GD25Q16ESIGR from GigaDevice Semicon Beijing, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CS#	input	Chip Select input, active low. Must be driven high when the device is not selected; do not leave floating after power-on. Selects the flash for all SPI/Dual/Quad transactions.
2	SO/IO1	bidirectional	Standard SPI serial data output (SO). In Dual/Quad SPI modes this pin becomes bidirectional data line IO1. Data is shifted out on the falling edge of SCLK.
3	WP#/IO2	bidirectional	Write Protect input (active low) that hardware-locks the status register when QE=0. When the non-volatile Quad Enable (QE) bit in the Status Register is set to 1, this pin becomes bidirectional Quad SPI data line IO2.
4	VSS	power_in	Ground reference for the device. Connect directly to system ground.
5	SI/IO0	bidirectional	Standard SPI serial data input (SI); latched on the rising edge of SCLK. In Dual/Quad SPI modes this pin becomes bidirectional data line IO0.
6	SCLK	input	Serial clock input; supports SPI modes 0 and 3, up to 133 MHz (with 30 pF load, VCC 3.0-3.6 V). Input data is latched on the rising edge and output data shifts on the falling edge.
7	HOLD#/IO3	bidirectional	Hold input (active low) that pauses serial communication without deselecting the device when QE=0. When QE=1, this pin becomes bidirectional Quad SPI data line IO3.
8	VCC	power_in	Single power supply, 2.7 V to 3.6 V (full voltage range). Requires local decoupling; device auto-resets below the write-inhibit threshold VWI.

Key specifications

Parameter	Value
Manufacturer	GigaDevice Semicon Beijing
Package	SOP-8-208mil
Category	Memory
Pins	8

Ordering variants

Same part, different packaging or reel option.

GD25Q16ESIGRETIG
GD25Q16ESIGRETJG
GD25Q16ESIGRETEG
GD25Q16ESIGRETFG
GD25Q16ESIGR
GD25Q16ESIGRESJG
GD25Q16ESIGRESEG
GD25Q16ESIGRESFG
GD25Q16ESIGREEIG
GD25Q16ESIGREEJG
GD25Q16ESIGREEEG
GD25Q16ESIGREEFG
GD25Q16ESIGRENIG
GD25Q16ESIGRENJG
GD25Q16ESIGRENEG
GD25Q16ESIGRENFG
GD25Q16ESIGREQIG
GD25Q16ESIGREQJG
GD25Q16ESIGREQEG
GD25Q16ESIGREQFG
GD25Q16ESIGREWIG
GD25Q16ESIGREWJG
GD25Q16ESIGREWEG
GD25Q16ESIGREWFG

CAD (KiCad official)

Symbol: GD25Q16ESIGR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8-208mil (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`gd25q16esigr.step`	122 KB	You want the bare part, or you mark your own boards.
`gd25q16esigr-etched.step`	2.6 MB	You want the part with `GD25Q16ESIGR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 637 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: GigaDevice Semicon Beijing datasheet (58 pp, sha256 e664882f90d940a2, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF