Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

FT24C64A-ELR-T

FMD Fremont Micro Devices · EEPROM · SOT-23-5

FT24C64A-ELR-T from FMD Fremont Micro Devices, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCL input Serial clock input. Rising edge latches data into the EEPROM; falling edge clocks data out. Schmitt-triggered/filtered input. Requires an external pull-up resistor to VCC (typical bus pull-up ~1.3kOhm per AC test conditions).
2 GND power_in Device ground reference (0V).
3 SDA bidirectional Serial data line. Bi-directional, open-drain output; can be wired-OR with other open-drain devices. Requires an external pull-up resistor to VCC. Schmitt-triggered/filtered input.
4 VCC power_in Supply voltage, 1.8V to 5.5V. Requires a decoupling capacitor of at least 10nF and a monotonic power-up ramp between 0.05 V/us and 0.1 V/ms. Read current typ 0.4mA / max 1.0mA; write current typ 2.0mA / max 3.0mA; standby <1uA.
5 WP input Write Protect. When tied to VIH or VCC, all programming/write operations are disabled (read is unaffected). When left unconnected or tied to VIL, writes are permitted (internal pull-down interprets an open pin as VIL).

Key specifications

Parameter Value
Manufacturer FMD Fremont Micro Devices
Package SOT-23-5
Category Memory
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • FT24C64A-ELR-T
  • FT24C64A-ELR-TELG-T
  • FT24C64A-ELR-TEPR-T
  • FT24C64A-ELR-TEPG-T
  • FT24C64A-ELR-TEDR-B
  • FT24C64A-ELR-TEDG-B
  • FT24C64A-ELR-TESR-B
  • FT24C64A-ELR-TESR-T
  • FT24C64A-ELR-TESG-B
  • FT24C64A-ELR-TESG-T
  • FT24C64A-ELR-TEMR-B
  • FT24C64A-ELR-TEMR-T
  • FT24C64A-ELR-TEMG-B
  • FT24C64A-ELR-TEMG-T
  • FT24C64A-ELR-TETR-B
  • FT24C64A-ELR-TETR-T
  • FT24C64A-ELR-TETG-B
  • FT24C64A-ELR-TETG-T
  • FT24C64A-ELR-TENR-T
  • FT24C64A-ELR-TENG-T

CAD (KiCad official)

  • Symbol: FT24C64A-ELR-T
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: ft24c64a-elr-t-etched.step / ft24c64a-elr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft24c64a-elr-t.step / ft24c64a-elr-t.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ft24c64a-elr-t.step 85 KB You want the bare part, or you mark your own boards.
ft24c64a-elr-t-etched.step 1.9 MB You want the part with FT24C64A-ELR-T already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 487 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FMD Fremont Micro Devices datasheet (19 pp, sha256 33ca3f890ea0488c, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF