component
EA9206
Public Made by Adomby adom
Everanalog IC design DC-DC Converters, TSOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownEA9206
Everanalog IC design · DC-DC Converters · TSOT-23-6
EA9206 from Everanalog IC design, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin. Common return for the internal power stage and control circuitry; connect to the system ground plane with a low-impedance path. |
| 2 | LX | output | Power switching node between the internal high-side and low-side MOSFETs. Connect the external inductor here; swings between roughly GND and VIN at the switching frequency (~500kHz). |
| 3 | VIN | power_in | Power supply input, 4.5V to 20V (absolute max 22V). Place input decoupling capacitors as close as possible from VIN to GND to minimize switching noise. |
| 4 | FB | input | Voltage feedback input. Tie to VOUT via a resistor divider; the internal reference regulates this pin at 0.768V (typ). Input current is ~10nA (0.1μA max). |
| 5 | SHDN | input | Active-low shutdown / enable input (bar-labeled SHDN). Drive above ~1.5V to enable the regulator, below 0.5V to shut it down (<1μA shutdown current). Connect to VIN through a 100kΩ resistor for auto start-up. Absolute max 22V. |
| 6 | BST | passive | High-side gate-drive bootstrap pin. Connect a 100nF to 1μF ceramic capacitor from BST to LX to boost the drive voltage that fully enhances the internal high-side NMOS. Absolute max VLX + 6.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everanalog IC design |
| Package | TSOT-23-6 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
EA9206S9
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage VIN (recommended) | VIN | 4.5 | 20 | V | 4 | ||
| Operation Temperature Range | -40 | 85 | °C | 4 | |||
| Supply Voltage VIN (absolute maximum) | VIN | -0.3 | 22 | V | 4 | ||
| Enable Voltage H (absolute maximum) | -0.3 | 22 | V | 4 | |||
| LX Voltage (absolute maximum) | VLX | -0.3 | V | Printed maximum is (VIN +0.3V) | 4 | ||
| Dynamic LX Voltage (absolute maximum) | -5 | V | 15ns duration; printed maximum is VIN +5V | 4 | |||
| BST Pin Voltage (absolute maximum) | VBST | -0.3 | V | Printed maximum is (VLX +6.5V) | 4 | ||
| All Other Pins Voltage (absolute maximum) | -0.3 | 6 | V | 4 | |||
| Maximum Junction Temperature (absolute maximum) | TJ | 150 | °C | 4 | |||
| Storage Temperature (absolute maximum) | TS | -65 | 150 | °C | 4 | ||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10sec. | 4 | |||
| VIN Quiescent Current | IDDQ | 0.3 | mA | H =2V, VFB=1V | 5 | ||
| VIN Shutdown Supply Current | ISD | 0.1 | 1 | μA | H =0V | 5 | |
| Feedback Voltage | VFB | 0.757 | 0.768 | 0.779 | V | 4.5V≦VIN≦18V | 5 |
| Feedback Input Current | IFB | 0.01 | 0.1 | μA | VFB=1V | 5 | |
| Valley Current Limit | ILIMIT | 4 | A | 5 | |||
| On Time | TON | 175 | ns | VIN=12V, VOUT=1.05V | 5 | ||
| Minimum Off Time | TOFF(MIN) | 200 | ns | VFB=0.4V | 5 | ||
| Input Supply Voltage UVLO Threshold | VUVLO(Vth) | 3.7 | 4 | 4.3 | V | VIN Rising | 5 |
| UVLO Threshold Hysteresis | VUVLO(HYS) | 0.25 | V | 5 | |||
| Internal Soft-Start Period | TSS | 1 | ms | Note 3 (not production tested) | 5 | ||
| EN Input Low Voltage | 0.5 | V | 5 | ||||
| EN Input High Voltage | 1.5 | V | 5 | ||||
| EN Input Current | 2 | μA | H =2V | 5 | |||
| Thermal Shutdown Threshold | TSD | 160 | °C | Note 3 (not production tested) | 5 | ||
| Thermal Shutdown Hysteresis | THYS | 30 | °C | Note 3 (not production tested) | 5 | ||
| Package Thermal Resistance (θJA) | θJA | 85 | °C/W | TSOT-23-6; measured at 25°C ambient on JEDEC-51-7 4-layer board | 4 | ||
| Package Thermal Resistance (θJC) | θJC | 20 | °C/W | TSOT-23-6 | 4 |
CAD (KiCad official)
- Symbol:
EA9206 - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
ea9206-etched.step/ea9206-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ea9206.step/ea9206.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
ea9206.step |
97 KB | You want the bare part, or you mark your own boards. |
ea9206-etched.step |
1.5 MB | You want the part with EA9206 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 363 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Everanalog IC design datasheet (9 pp, sha256
e5cd859b78efd289, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).