EA8212LT6R from Everanalog IC design, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT	power_in	Bootstrap supply for the internal high-side N-MOSFET gate driver. Connect a 33nF ceramic capacitor from BOOT to SWITCH to develop the boosted rail (VSWITCH-0.3V to VSWITCH+6.3V absolute max).
2	GND	power_in	Device ground return for the low-side power MOSFET and analog control circuitry. Tie to the system ground plane with a short, wide trace.
3	FBK	input	Feedback input to the internal error amplifier (VREF = 0.6V typ). Connect a resistor divider from VOUT to FBK to GND; VOUT = 0.6V x (1 + R1/R2). Absolute max -0.3V to +6.3V.
4	RUN	input	Enable / shutdown control input. Drive above 2V (VRUN-H) to enable the regulator; drive below 0.4V (VRUN-L) to shut down (ISD < 10uA typ). Tie to PWR through a 150K resistor for automatic startup. Absolute max -0.3V to +17V.
5	PWR	power_in	Main power input to the buck converter, 4.5V to 16V operating (17V absolute max, 19V OVP threshold). Decouple with two 10uF X5R/X7R MLCC capacitors between PWR and GND placed close to the pin.
6	SWITCH	output	Switch node output from the internal high-side / low-side power MOSFETs (RDS(on) 90 mOhm HS / 70 mOhm LS, ILIM 2.5A min). Connect to the output inductor of the L-C low-pass filter to generate the regulated DC output. Absolute max -1V to +17.5V.

Key specifications

Parameter	Value
Manufacturer	Everanalog IC design
Package	SOT-23-6
Category	PMIC
Pins	6

Ordering variants

Same part, different packaging or reel option.

EA8212LT6R

CAD (KiCad official)

Symbol: EA8212LT6R
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`ea8212lt6r.step`	97 KB	You want the bare part, or you mark your own boards.
`ea8212lt6r-etched.step`	1.9 MB	You want the part with `EA8212LT6R` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 468 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Everanalog IC design datasheet (9 pp, sha256 c2c15b39687453d1, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF