DM9161AEP from DAVICOM, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDDR	power_in	Analog receive supply, +3.3V nominal. Decouple locally with 100nF and a ferrite/pi-filter from the main analog rail.
2	AVDDR	power_in	Analog receive supply, +3.3V nominal (second pin of the AVDDR net). Decouple locally with 100nF.
3	RX+	input	Differential receive pair positive input from the magnetics/RJ45 (100Ω differential). Carries data recovered from the media.
4	RX-	input	Differential receive pair negative input from the magnetics/RJ45 (100Ω differential).
5	AGND	power_in	Analog receive ground. Tie to the analog ground plane.
6	AGND	power_in	Analog transmit ground. Tie to the analog ground plane.
7	TX+	output	Differential transmit pair positive output to the magnetics (100BASE-TX MLT-3 or 10BASE-T Manchester). Drives 1:1 or 1.25:1 transformer.
8	TX-	output	Differential transmit pair negative output to the magnetics.
9	AVDDT	power_in	Analog transmit supply, +3.3V nominal. Decouple locally with 100nF and a ferrite from the analog rail.
10	PWRDWN	input	Power-down control (active high). When high, most blocks power off; only MDC/MDIO management remains active. A hardware or software reset with PWRDWN low is required to exit power-down.
11	LED0/OP0	bidirectional	LED driver output 0 (post-reset). During power-up/reset it is latched as OP0, one of the mode-select strap bits per Table A (media type selection). Weak internal pull-up.
12	LED1/OP1	bidirectional	LED driver output 1 (post-reset). Latched as OP1 mode-select strap at reset per Table A. Weak internal pull-up.
13	LED2/OP2	bidirectional	LED driver output 2 (post-reset). Latched as OP2 mode-select strap at reset per Table A. Weak internal pull-up.
14	CABLESTS/LINKSTS	bidirectional	Cable-status or link-status output. Function selected by the reset latch state: latch low = cable-status (1 = cable present), latch high = link-status (0 = link up). Weak internal pull-down.
15	DGND	power_in	Digital ground. Tie to the digital ground plane.
16	TXER/TXD[4]	input	Transmit Error in 100BASE-TX MII mode (active high injects HALT symbol). Ignored in 10Mbps. In 4B/5B bypass mode this pin carries the 5th TXD[4] data bit.
17	TXD[3]	input	MII transmit data bit 3, synchronous to TXCLK in 10/100Mbps nibble mode. Ignored in 10Mbps GPSI 7-wired mode.
18	TXD[2]	input	MII transmit data bit 2, synchronous to TXCLK in 10/100Mbps nibble mode. Ignored in 10Mbps GPSI 7-wired mode.
19	TXD[1]	input	MII transmit data bit 1, synchronous to TXCLK in 10/100Mbps nibble mode. Ignored in 10Mbps GPSI 7-wired mode.
20	TXD[0]	input	MII transmit data bit 0, synchronous to TXCLK in 10/100Mbps nibble mode. Serves as the serial transmit data input in 10Mbps GPSI 7-wired mode.
21	TXEN	input	Transmit Enable (active high). Indicates valid nibble data on TXD[3:0] in 100Mbps and 10Mbps nibble modes, or valid serial data on TXD[0] in 10Mbps GPSI 7-wired mode.
22	TXCLK/ISOLATE	tri_state	Transmit clock output from the PHY: 25MHz in 100Mbps MII, 2.5MHz in 10Mbps MII, 10MHz in 10Mbps GPSI. Also latched at reset as ISOLATE (0 = normal, 1 = MII isolate, Reg 0.10 = 1). Weak internal pull-down at reset.
23	DVDD	power_in	Digital I/O supply, +3.3V nominal (5V tolerant I/Os). Decouple locally with 100nF.
24	MDC	input	Management data clock provided by the MAC/STA, up to 12.5MHz. Clocks the MDIO serial management interface.
25	MDIO	bidirectional	Management data I/O, bidirectional serial data for accessing PHY MII registers. Requires an external ~1.5kΩ pull-up.
26	RXD[3]/PHYAD[3]	tri_state	MII receive data bit 3, synchronous to RXCLK. Also latched at power-up/reset as PHYAD[3], part of the PHY address strap. Weak internal pull-down at reset.
27	RXD[2]/PHYAD[2]	tri_state	MII receive data bit 2, synchronous to RXCLK. Latched at reset as PHYAD[2]. Weak internal pull-down at reset.
28	RXD[1]/PHYAD[1]	tri_state	MII receive data bit 1, synchronous to RXCLK. Latched at reset as PHYAD[1]. Weak internal pull-down at reset.
29	RXD[0]/PHYAD[0]	tri_state	MII receive data bit 0, synchronous to RXCLK. In 10Mbps GPSI 7-wired mode this pin is the serial data output. Latched at reset as PHYAD[0]. Weak internal pull-down at reset.
30	DVDD	power_in	Digital I/O supply, +3.3V nominal. Decouple locally with 100nF.
31	LEDMODE	input	LED mode select input. 0 = dual-LED mode, 1 = normal LED mode; picks how LED0..LED3 encode link/activity/speed/duplex.
32	MDINTR#	tri_state	Status interrupt output. Asserted on link/speed/duplex change per interrupt register 21. Active polarity is programmable (asserts low when pulled up, high when pulled down). Weak internal pull-down at reset.
33	DGND	power_in	Digital ground.
34	RXCLK/10BTSER	tri_state	Receive clock output from the PHY: 25MHz in 100Mbps MII, 2.5MHz in 10Mbps MII, 10MHz in 10Mbps GPSI. Latched at reset as 10BTSER (0 = 10Mbps GPSI, 1 = 10Mbps MII). Weak internal pull-up at reset.
35	CRS/PHYAD[4]	tri_state	Carrier-Sense output (active high) indicating TX or RX activity in half-duplex; in full-duplex/repeater asserts only for RX activity. Latched at reset as PHYAD[4], the top PHY-address bit. Weak internal pull-down at reset.
36	COL/RMII	tri_state	Collision detection output (asserted high in 10/100Mbps half-duplex; always 0 in full-duplex). Latched at reset as RMII enable: 0 = Normal MII, 1 = Reduced MII. Weak internal pull-down.
37	RXDV/TESTMODE	tri_state	Receive Data Valid, asserted high while RXD[3:0] carries valid data. Latched at reset as TESTMODE (0 = normal, 1 = test mode). Weak internal pull-down at reset.
38	RXER/RXD[4]/RPTR	tri_state	Receive Error output in MII mode; asserted on invalid symbol. In 4B/5B decoder-bypass mode becomes RXD[4]. Latched at reset as RPTR: 0 = Node mode, 1 = Repeater mode. Weak internal pull-down at reset.
39	DISMDIX	input	HP Auto-MDIX control input. 0 = enable Auto-MDIX crossover detection, 1 = disable Auto-MDIX (fixed MDI). Weak internal pull-down.
40	RESET#	input	Active-low hardware reset input. Holds the DM9161A in reset while low; releases to initialize registers and latch reset-strap inputs.
41	DVDD	power_in	Digital I/O supply, +3.3V nominal.
42	XT2	bidirectional	25MHz crystal output; also serves as the 50MHz REF_CLK single-ended input when the PHY is used in RMII mode.
43	XT1	input	25MHz crystal input (XT1-XT2 across a parallel-resonant crystal with load capacitors).
44	DGND	power_in	Digital ground.
45	NC	unconnected	No connect. Leave floating or tie to ground per Davicom reference design.
46	AGND	power_in	Analog substrate ground. Tie to the analog ground plane.
47	BGRESG	passive	Bandgap reference resistor ground return. Connects one end of the external 6.8kΩ ±1% bandgap reference resistor to analog ground.
48	BGRES	passive	Bandgap voltage reference. Tie an external 6.8kΩ ±1% resistor between BGRES and BGRESG to set the internal bias current.

Key specifications

Parameter	Value
Manufacturer	DAVICOM
Package	LQFP-48(7x7)
Category	Interface
Pins	48

Ordering variants

Same part, different packaging or reel option.

DM9161AEP

CAD (KiCad official)

Symbol: DM9161AEP
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`dm9161aep.step`	617 KB	You want the bare part, or you mark your own boards.
`dm9161aep-etched.step`	3.7 MB	You want the part with `DM9161AEP` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 959 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: DAVICOM datasheet (45 pp, sha256 166788920e65d687, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF