DG409DY-T1-E3 from Vishay, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A0	input	Address bit 0 (LSB). TTL-compatible logic input selecting the active channel (Logic 0 = VAL ≤ 0.8 V, Logic 1 = VAH ≥ 2.4 V). Input current ±10 µA max.
2	EN	input	Enable input, TTL-compatible. When Logic 0 all switches are OFF; when Logic 1 the switch selected by A0/A1 is ON. Allows stacking of multiple devices.
3	V-	power_in	Negative analog supply. Dual-supply operation ±5 V to ±20 V, or connect to GND for single-supply operation (+5 V to +36 V referenced to V-). Analog signal range V- to V+.
4	S1a	passive	Analog switch source, bank A channel 1. Bidirectional analog terminal connected to Da when A1=0, A0=0, EN=1. RDS(on) ~100 Ω (V±=±15 V).
5	S2a	passive	Analog switch source, bank A channel 2. Bidirectional analog terminal connected to Da when A1=0, A0=1, EN=1.
6	S3a	passive	Analog switch source, bank A channel 3. Bidirectional analog terminal connected to Da when A1=1, A0=0, EN=1.
7	S4a	passive	Analog switch source, bank A channel 4. Bidirectional analog terminal connected to Da when A1=1, A0=1, EN=1.
8	Da	passive	Analog switch drain, bank A common. Bidirectional analog terminal common to S1a-S4a. Peak S/D current 100 mA pulsed; 30 mA continuous per terminal.
9	Db	passive	Analog switch drain, bank B common. Bidirectional analog terminal common to S1b-S4b.
10	S4b	passive	Analog switch source, bank B channel 4. Bidirectional analog terminal connected to Db when A1=1, A0=1, EN=1.
11	S3b	passive	Analog switch source, bank B channel 3. Bidirectional analog terminal connected to Db when A1=1, A0=0, EN=1.
12	S2b	passive	Analog switch source, bank B channel 2. Bidirectional analog terminal connected to Db when A1=0, A0=1, EN=1.
13	S1b	passive	Analog switch source, bank B channel 1. Bidirectional analog terminal connected to Db when A1=0, A0=0, EN=1.
14	V+	power_in	Positive analog supply. Dual-supply ±5 V to ±20 V, or single-supply +5 V to +36 V (referenced to V-). Absolute max V+ to V- = 44 V. Quiescent I+ typ 10 µA (dual supply).
15	GND	power_in	Digital ground reference for A0, A1, EN logic thresholds. GND to V- limited to -25 V absolute max.
16	A1	input	Address bit 1 (MSB). TTL-compatible logic input selecting the active channel with A0 (see truth table). Input current ±10 µA max.

Key specifications

Parameter	Value
Manufacturer	Vishay
Package	SOIC-16
Category	Interface
Pins	16

Ordering variants

Same part, different packaging or reel option.

DG409DY-T1-E3
DG409DY-E3
DG409DJ
DG409DJ-E3
DG409DQ-E3
DG409DQ-T1-E3

CAD (KiCad official)

Symbol: DG409DY-T1-E3
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`dg409dy-t1-e3.step`	217 KB	You want the bare part, or you mark your own boards.
`dg409dy-t1-e3-etched.step`	2.6 MB	You want the part with `DG409DY-T1-E3` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 662 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Vishay datasheet (17 pp, sha256 74df98dee9139dfa, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF