Four independent 16-bit voltage-output DACs in one package, driven over SPI, with an internal 2.5 V reference so no external reference is needed for a defined full scale. It holds true 16-bit accuracy (monotonic, low INL), and a per-channel gain plus a global reference-divide set output spans from the reference or twice it. LDAC and RSTSEL manage synchronous updates and power-on state. A compact precision source for calibration, bias, and control loops.

Pinout

Pin	Name	Type	Function
1	REF	bidirectional	Reference pin. When using the internal reference this is the reference output voltage pin (default). When using an external reference this is the reference input pin.
2	OUT0	output	Analog output voltage from DAC channel 0. Buffered, high-drive (up to 20 mA within 0.5 V of the rails).
3	OUT1	output	Analog output voltage from DAC channel 1. Buffered voltage output.
4	OUT2	output	Analog output voltage from DAC channel 2. Buffered voltage output.
5	OUT3	output	Analog output voltage from DAC channel 3. Buffered voltage output.
6	GND	power_in	Ground reference point for all circuitry on the device.
7	VDD	power_in	Analog supply voltage, 2.7 V to 5.5 V.
8	GAIN	input	Sets the gain configuration after power-up or reset. Tied to GND -> buffer gain = 1 for all four channels. Tied to VIO -> buffer gain = 2. Changes after power-up have no effect.
9	RSTSEL	input	Reset select. Tied to GND -> all four DACs reset to zero scale. Tied to VIO -> all four DACs reset to midscale.
10	REFDIV	input	Sets the reference divider configuration after power-up or reset. Tied to GND -> reference not divided. Tied to VIO -> reference voltage divided by 2. Changes after power-up have no effect.
11	LDAC	input	Load-DAC. Active-low. A high-to-low transition causes DAC outputs of channels configured in synchronous mode to update simultaneously. May be tied permanently to GND.
12	CS	input	Active-low serial-interface frame synchronization (chip select). When low, enables the SPI input shift register.
13	SCLK	input	Serial interface clock, up to 50 MHz.
14	SDI	input	Serial interface data input. Data are clocked into the input shift register on each falling edge of SCLK.
15	SDO/ALARM	output	Serial data output (default). SDO is high impedance when CS is high. Data are clocked out of the shift register on either the rising or falling edge of SCLK as specified by the FSDO bit. Alternatively can be configured as an open-drain ALARM output to indicate a CRC or reference alarm event; when used as ALARM a 10 kΩ pull-up to VIO is required.
16	VIO	power_in	I/O supply voltage, 1.7 V to 5.5 V. Sets the I/O operating voltage for the serial interface.
17	Thermal Pad	passive	Exposed thermal pad on the bottom of the QFN package. Connect to internal PCB ground plane with multiple vias for good thermal performance.

Key specifications

Parameter	Value
Type	Quad-channel voltage-output DAC
Resolution	16-bit
Channels	4
Interface	SPI
Reference	Internal 2.5 V or external
Accuracy	16-bit monotonic, low INL
Supply	2.7-5.5 V
Package	WQFN-16

Ordering variants

Same part, different packaging or reel option.

DAC80504RTER (WQFN-16)
DAC80504PW (TSSOP-16)

CAD (KiCad official)

Symbol: Analog_DAC:DAC80504 (KiCad official)
Footprint: Package_DFN_QFN:Texas_RTE0016D_WQFN-16-1EP_3x3mm_P0.5mm_EP0.8x0.8mm_ThermalVias
3D model: WQFN-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (50 pp, sha256 66feb81f28eb3a23, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF