CN3125 from ShangHai Consonance Elec, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CE	input	Chip Enable. A logic high enables normal operation; pulling CE low puts the CN3125 into disable mode and the whole device is turned off. TTL/CMOS compatible (VCEH >= 2.2V, VCEL <= 0.7V).
2	ISET	passive	Constant charge current setting and charge current monitor pin. Charge current is programmed by a resistor R_ISET from this pin to GND; V_ISET is regulated to 1.205V in constant-current mode. Charge current: ICH = (V_ISET / R_ISET) x 986.
3	GND	power_in	Ground terminal.
4	VIN	power_in	Positive input supply voltage (2.7V to 6V, absolute max 6.5V). Powers internal circuitry and the on-chip P-channel power MOSFET. When VIN drops within 10mV of the TOP pin voltage, the part enters low-power sleep mode (TOP/MID current < 3uA).
5	TOP	power_out	Positive terminal connection to the top supercapacitor. Charge current is delivered from this pin. For 2-cell configuration, connect to the positive terminal of the top supercap; for single-cell, tie the single supercap between TOP and GND. Continuous short-circuit tolerant.
6	MID	bidirectional	Middle connection of the 2 supercapacitors. The negative terminal of the top supercap and the positive terminal of the bottom supercap connect here. Sources/sinks active cell-balancing shunt current (I_SHTOP up to ~55mA typ, I_SHBOT up to ~50mA typ). Continuous short-circuit tolerant.
7	PG	output	Open-drain Power Good output (active-low, /PG). Pulls low when the supercapacitor voltage rises above ~94.1% of the final regulated voltage set at FB, and returns to high-impedance when it falls below ~90%. High-impedance when disabled or in sleep mode. Sink current up to 10mA at V_PG = 0.3V.
8	FB	input	Supercapacitor voltage feedback pin. The constant-voltage regulation point is set by an external resistor divider tied from TOP (or MID for single-cell) to FB to GND; internal reference V_REGFB = 1.205V (1.193-1.217V). Leakage +/-100nA max.
9	EP	power_in	Exposed thermal pad on the underside of the eSOP-8 package. Must be soldered to the GND plane for proper electrical grounding and heat dissipation.

Key specifications

Parameter	Value
Manufacturer	ShangHai Consonance Elec
Package	ESOP-8
Category	PMIC
Pins	9

Ordering variants

Same part, different packaging or reel option.

CN3125

CAD (KiCad official)

Symbol: CN3125
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
3D model: ESOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cn3125.step`	193 KB	You want the bare part, or you mark your own boards.
`cn3125-etched.step`	1.2 MB	You want the part with `CN3125` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 303 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ShangHai Consonance Elec datasheet (11 pp, sha256 01642d3ae17a657f, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF