CD74HC595M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QB	tri_state	3-state parallel output bit B of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
2	QC	tri_state	3-state parallel output bit C of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
3	QD	tri_state	3-state parallel output bit D of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
4	QE	tri_state	3-state parallel output bit E of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
5	QF	tri_state	3-state parallel output bit F of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
6	QG	tri_state	3-state parallel output bit G of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
7	QH	tri_state	3-state parallel output bit H (MSB) of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
8	GND	power_in	Ground reference (0 V) for the device.
9	QH'	output	Serial data output from the last stage of the shift register (not 3-state). Used to cascade multiple CD74HC595 devices by connecting QH' to the SER input of the next stage.
10	SRCLR	input	Active-low direct overriding shift-register clear. When held low, the shift register is asynchronously cleared; the storage register is unaffected.
11	SRCLK	input	Shift-register clock input. On each positive edge, serial data on SER is shifted into the 8-bit shift register.
12	RCLK	input	Storage-register (latch) clock input. On each positive edge, the contents of the shift register are transferred to the 8-bit storage register and appear at QA-QH.
13	OE	input	Active-low output-enable for the QA-QH 3-state outputs. When high, QA-QH are placed in the high-impedance state; when low, storage-register data drives the outputs. Does not affect QH'.
14	SER	input	Serial data input to the first stage of the shift register. Sampled on the positive edge of SRCLK.
15	QA	tri_state	3-state parallel output bit A (LSB) of the 8-bit storage register. Drives up to ±6 mA at VCC = 5 V; high-impedance when OE is high.
16	VCC	power_in	Positive supply voltage input. Recommended operating range 2 V to 6 V (5 V nominal); absolute maximum 7 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD74HC595M96M
CD74HC595M96
CD74HC595M96MT
CD74HC595M96DW
CD74HC595M96DWR
CD74HC595M96E
CD74HC595M96NSR
CD74HC595M96SM
CD74HC595M96SM96

CAD (KiCad official)

Symbol: CD74HC595M96
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd74hc595m96.step`	217 KB	You want the bare part, or you mark your own boards.
`cd74hc595m96-etched.step`	2.9 MB	You want the part with `CD74HC595M96` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 706 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (22 pp, sha256 e9237e04a8fe62ec, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF